AT91SAM7X128 Atmel, AT91SAM7X128 Datasheet - Page 278
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AT91SAM7X128
Manufacturer Part Number
AT91SAM7X128
Description
MCU 32-Bit 91S ARM7TDMI RISC 128KB Flash 1.8V/3.3V 100-Pin LQFP
Manufacturer
Atmel
Datasheet
1.AT91SAM7X512-AU-999.pdf
(687 pages)
Specifications of AT91SAM7X128
Package
100LQFP
Device Core
ARM7TDMI
Family Name
91S
Maximum Speed
55 MHz
Ram Size
32 KB
Program Memory Size
128 KB
Operating Supply Voltage
1.8|3.3 V
Data Bus Width
32 Bit
Program Memory Type
Flash
Number Of Programmable I/os
62
Interface Type
CAN/Ethernet/SPI/I2S/TWI/USART/USB
On-chip Adc
8-chx10-bit
Operating Temperature
-40 to 85 °C
Number Of Timers
3
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28.7.9
Name:
Access Type:
• CPOL: Clock Polarity
0 = The inactive state value of SPCK is logic level zero.
1 = The inactive state value of SPCK is logic level one.
CPOL is used to determine the inactive state value of the serial clock (SPCK). It is used with NCPHA to produce the
required clock/data relationship between master and slave devices.
• NCPHA: Clock Phase
0 = Data is changed on the leading edge of SPCK and captured on the following edge of SPCK.
1 = Data is captured on the leading edge of SPCK and changed on the following edge of SPCK.
NCPHA determines which edge of SPCK causes data to change and which edge causes data to be captured. NCPHA is
used with CPOL to produce the required clock/data relationship between master and slave devices.
• CSAAT: Chip Select Active After Transfer
0 = The Peripheral Chip Select Line rises as soon as the last transfer is achieved.
1 = The Peripheral Chip Select does not rise after the last transfer is achieved. It remains active until a new transfer is
requested on a different chip select.
• BITS: Bits Per Transfer
The BITS field determines the number of data bits transferred. Reserved values should not be used.
278
31
23
15
7
AT91SAM7X512/256/128 Preliminary
SPI Chip Select Register
SPI_CSR0... SPI_CSR3
Read-write
30
22
14
6
BITS
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
BITS
29
21
13
5
28
20
12
4
DLYBCT
DLYBS
SCBR
CSAAT
27
19
11
3
Bits Per Transfer
26
18
10
2
–
Reserved
Reserved
Reserved
10
11
12
13
14
15
16
8
9
NCPHA
25
17
9
1
6120H–ATARM–17-Feb-09
CPOL
24
16
8
0
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