AT91SAM7X128 Atmel, AT91SAM7X128 Datasheet - Page 65
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AT91SAM7X128
Manufacturer Part Number
AT91SAM7X128
Description
MCU 32-Bit 91S ARM7TDMI RISC 128KB Flash 1.8V/3.3V 100-Pin LQFP
Manufacturer
Atmel
Datasheet
1.AT91SAM7X512-AU-999.pdf
(687 pages)
Specifications of AT91SAM7X128
Package
100LQFP
Device Core
ARM7TDMI
Family Name
91S
Maximum Speed
55 MHz
Ram Size
32 KB
Program Memory Size
128 KB
Operating Supply Voltage
1.8|3.3 V
Data Bus Width
32 Bit
Program Memory Type
Flash
Number Of Programmable I/os
62
Interface Type
CAN/Ethernet/SPI/I2S/TWI/USART/USB
On-chip Adc
8-chx10-bit
Operating Temperature
-40 to 85 °C
Number Of Timers
3
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13.2.4.5
6120H–ATARM–17-Feb-09
Watchdog Reset
The Watchdog Reset is entered when a watchdog fault occurs. This state lasts 3 Slow Clock
cycles.
When in Watchdog Reset, assertion of the reset signals depends on the WDRPROC bit in
WDT_MR:
The Watchdog Timer is reset by the proc_nreset signal. As the watchdog fault always causes a
processor reset if WDRSTEN is set, the Watchdog Timer is always reset after a Watchdog
Reset, and the Watchdog is enabled by default and with a period set to a maximum.
When the WDRSTEN in WDT_MR bit is reset, the watchdog fault has no impact on the reset
controller.
Figure 13-8. Watchdog Reset
• If WDRPROC is 0, the Processor Reset and the Peripheral Reset are asserted. The NRST
• If WDRPROC = 1, only the processor reset is asserted.
WDRPROC = 0
line is also asserted, depending on the programming of the field ERSTL. However, the
resulting low level on NRST does not result in a User Reset state.
Only if
periph_nreset
proc_nreset
(nrst_out)
RSTTYP
wd_fault
NRST
SLCK
MCK
AT91SAM7X512/256/128 Preliminary
Freq.
Any
Any
Processor Startup
= 3 cycles
XXX
EXTERNAL RESET LENGTH
8 cycles (ERSTL=2)
0x2 = Watchdog Reset
65
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