AT91SAM7X128 Atmel, AT91SAM7X128 Datasheet - Page 281

• Manufacturer Part Number: AT91SAM7X128
• Description: MCU 32-Bit 91S ARM7TDMI RISC 128KB Flash 1.8V/3.3V 100-Pin LQFP
• Manufacturer: Atmel

Specifications of AT91SAM7X128

• Package: 100LQFP
• Device Core: ARM7TDMI
• Family Name: 91S
• Maximum Speed: 55 MHz
• Ram Size: 32 KB
• Program Memory Size: 128 KB
• Operating Supply Voltage: 1.8|3.3 V
• Data Bus Width: 32 Bit
• Program Memory Type: Flash
• Number Of Programmable I/os: 62
• Interface Type: CAN/Ethernet/SPI/I2S/TWI/USART/USB
• On-chip Adc: 8-chx10-bit
• Operating Temperature: -40 to 85 °C
• Number Of Timers: 3

29. Two-wire Interface (TWI)
29.1
29.2
6120H–ATARM–17-Feb-09
Overview
Block Diagram
The Two-wire Interface (TWI) interconnects components on a unique two-wire bus, made up of
one clock line and one data line with speeds of up to 400 Kbits per second, based on a byte-ori-
ented transfer format. It can be used with any Atmel Two-wire Interface bus Serial EEPROM and
I²C compatible device such as Real Time Clock (RTC), Dot Matrix/Graphic LCD Controllers and
Temperature Sensor, to name but a few. The TWI is programmable as master transmitter or
master receiver with sequential or single-byte access. A configurable baud rate generator per-
mits the output data rate to be adapted to a wide range of core clock frequencies. Below,
29-1
Table 29-1.
Notes:
Figure 29-1. Block Diagram
I2C Standard
Standard Mode Speed (100 KHz)
Fast Mode Speed (400 KHz)
7 or 10 bits Slave Addressing
START BYTE
Repeated Start (Sr) Condition
ACK and NACK Management
Slope control and input filtering (Fast mode)
Clock strectching
lists the compatibility level of the Atmel Two-wire Interface and a full I2C compatible device.
1. START + b000000001 + Ack + Sr
2. A repeated start condition is only supported in Master Receiver mode. See
”Internal Address” on page 286
(1)
Atmel TWI compatibility with i2C Standard
PMC
APB Bridge
MCK
AT91SAM7X512/256/128 Preliminary
Two-wire
Interface
Atmel TWI
Supported
Supported
Supported
Not Supported
Not Fully Supported
Supported
Not Supported
Supported
Interrupt
TWI
PIO
AIC
(2)
TWCK
TWD
Section 29.5.5
Table
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