AT91SAM7X128 Atmel, AT91SAM7X128 Datasheet - Page 285
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AT91SAM7X128
Manufacturer Part Number
AT91SAM7X128
Description
MCU 32-Bit 91S ARM7TDMI RISC 128KB Flash 1.8V/3.3V 100-Pin LQFP
Manufacturer
Atmel
Datasheet
1.AT91SAM7X512-AU-999.pdf
(687 pages)
Specifications of AT91SAM7X128
Package
100LQFP
Device Core
ARM7TDMI
Family Name
91S
Maximum Speed
55 MHz
Ram Size
32 KB
Program Memory Size
128 KB
Operating Supply Voltage
1.8|3.3 V
Data Bus Width
32 Bit
Program Memory Type
Flash
Number Of Programmable I/os
62
Interface Type
CAN/Ethernet/SPI/I2S/TWI/USART/USB
On-chip Adc
8-chx10-bit
Operating Temperature
-40 to 85 °C
Number Of Timers
3
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29.5.4
Figure 29-9. Master Read with Multiple Data Bytes
6120H–ATARM–17-Feb-09
TXCOMP
RXRDY
TWD
Master Receiver Mode
S
Write START Bit
DADR
The read sequence begins by setting the START bit. After the start condition has been sent, the
master sends a 7-bit slave address to notify the slave device. The bit following the slave address
indicates the transfer direction, 1 in this case (MREAD = 1 in TWI_MMR). During the acknowl-
edge clock pulse (9th pulse), the master releases the data line (HIGH), enabling the slave to pull
it down in order to generate the acknowledge. The master polls the data line during this clock
pulse and sets the NACK bit in the status register if the slave does not acknowledge the byte.
If an acknowledge is received, the master is then ready to receive data from the slave. After data
has been received, the master sends an acknowledge condition to notify the slave that the data
has been received except for the last data, after the stop condition. See
RXRDY bit is set in the status register, a character has been received in the receive-holding reg-
ister (TWI_RHR). The RXRDY bit is reset when reading the TWI_RHR.
When a single data byte read is performed, with or without internal address (IADR), the START
and STOP bits must be set at the same time. See
performed, with or without internal address (IADR), the STOP bit must be set after the next-to-
last data received. See
Figure 29-8. Master Read with One Data Byte
R
A
TXCOMP
DATA n
RXRDY
TWD
Figure
AT91SAM7X512/256/128 Preliminary
Read RHR
A
S
DATA n
Write START &
29-9. For Internal Address usage see
DATA (n+1)
STOP Bit
DADR
A
DATA (n+1)
Read RHR
R
DATA (n+m)-1
Figure
A
29-8. When a multiple data byte read is
DATA
DATA (n+m)-1
A
Read RHR
after next-to-last data read
DATA (n+m)
Read RHR
Section
Write STOP Bit
N
Figure
P
29.5.5.
N
29-9. When the
DATA (n+m)
Read RHR
P
285
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