AT91SAM7X128 Atmel, AT91SAM7X128 Datasheet - Page 545

• Manufacturer Part Number: AT91SAM7X128
• Description: MCU 32-Bit 91S ARM7TDMI RISC 128KB Flash 1.8V/3.3V 100-Pin LQFP
• Manufacturer: Atmel

Specifications of AT91SAM7X128

• Package: 100LQFP
• Device Core: ARM7TDMI
• Family Name: 91S
• Maximum Speed: 55 MHz
• Ram Size: 32 KB
• Program Memory Size: 128 KB
• Operating Supply Voltage: 1.8|3.3 V
• Data Bus Width: 32 Bit
• Program Memory Type: Flash
• Number Of Programmable I/os: 62
• Interface Type: CAN/Ethernet/SPI/I2S/TWI/USART/USB
• On-chip Adc: 8-chx10-bit
• Operating Temperature: -40 to 85 °C
• Number Of Timers: 3

36.8.6
Name:
Access Type:
Any modification on one of the fields of the CANBR register must be done while CAN module is disabled.
To compute the different Bit Timings, please refer to the
• PHASE2: Phase 2 segment
This phase is used to compensate the edge phase error.
Warning: PHASE2 value must be different from 0.
• PHASE1: Phase 1 segment
This phase is used to compensate for edge phase error.
• PROPAG: Programming time segment
This part of the bit time is used to compensate for the physical delay times within the network.
• SJW: Re-synchronization jump width
To compensate for phase shifts between clock oscillators of different controllers on bus. The controller must re-synchronize
on any relevant signal edge of the current transmission. The synchronization jump width defines the maximum of clock
cycles a bit period may be shortened or lengthened by re-synchronization.
• BRP: Baudrate Prescaler.
This field allows user to program the period of the CAN system clock to determine the individual bit timing.
The BRP field must be within the range [1, 0x7F], i.e., BRP = 0 is not authorized.
• SMP: Sampling Mode
0 = The incoming bit stream is sampled once at sample point.
1 = The incoming bit stream is sampled three times with a period of a MCK clock period, centered on sample point.
SMP Sampling Mode is automatically disabled if BRP = 0.
6120H–ATARM–17-Feb-09
31
23
15
–
–
–
7
–
CAN Baudrate Register
t
t
t
t
t
PHS2
PHS1
PRS
SJW
CSC
=
=
=
=
=
30
22
14
CAN_BR
Read-write
–
–
6
t
t
(
CSC
CSC
t
t
BRP
CSC
CSC
×
×
×
×
+
(
(
1
(
(
PROPAG
SJW
PHASE2
PHASE1
)
⁄
PHASE1
MCK
+
29
21
13
–
5
1
)
+
+
+
1
1
1
SJW
)
)
)
AT91SAM7X512/256/128 Preliminary
28
20
12
–
4
Section 36.6.4.1 “CAN Bit Timing Configuration” on page
BRP
27
19
11
–
–
3
–
26
18
10
–
2
PROPAG
PHASE2
25
17
–
9
1
SMP
24
16
8
0
512.
545