AT91SAM7X128 Atmel, AT91SAM7X128 Datasheet - Page 179
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AT91SAM7X128
Manufacturer Part Number
AT91SAM7X128
Description
MCU 32-Bit 91S ARM7TDMI RISC 128KB Flash 1.8V/3.3V 100-Pin LQFP
Manufacturer
Atmel
Datasheet
1.AT91SAM7X512-AU-999.pdf
(687 pages)
Specifications of AT91SAM7X128
Package
100LQFP
Device Core
ARM7TDMI
Family Name
91S
Maximum Speed
55 MHz
Ram Size
32 KB
Program Memory Size
128 KB
Operating Supply Voltage
1.8|3.3 V
Data Bus Width
32 Bit
Program Memory Type
Flash
Number Of Programmable I/os
62
Interface Type
CAN/Ethernet/SPI/I2S/TWI/USART/USB
On-chip Adc
8-chx10-bit
Operating Temperature
-40 to 85 °C
Number Of Timers
3
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24.3.5
24.4
24.4.1
6120H–ATARM–17-Feb-09
Divider and PLL Block
Main Oscillator Bypass
PLL Filter
Slow Clock, so that the frequency of the crystal connected on the Main Oscillator can be
determined.
The user can input a clock on the device instead of connecting a crystal. In this case, the user
has to provide the external clock signal on the XIN pin. The input characteristics of the XIN pin
under these conditions are given in the product electrical characteristics section. The program-
mer has to be sure to set the OSCBYPASS bit to 1 and the MOSCEN bit to 0 in the Main OSC
register (CKGR_MOR) for the external clock to operate properly.
The PLL embeds an input divider to increase the accuracy of the resulting clock signals. How-
ever, the user must respect the PLL minimum input frequency when programming the divider.
Figure 24-3
Figure 24-3. Divider and PLL Block Diagram
The PLL requires connection to an external second-order filter through the PLLRC pin.
24-4
Figure 24-4. PLL Capacitors and Resistors
Values of R, C1 and C2 to be connected to the PLLRC pin must be calculated as a function of
the PLL input frequency, the PLL output frequency and the phase margin. A trade-off has to be
found between output signal overshoot and startup time.
shows a schematic of these filters.
shows the block diagram of the divider and PLL block.
MAINCK
AT91SAM7X512/256/128 Preliminary
SLCK
C2
Divider
DIV
C1
R
PLLRC
GND
PLLCOUNT
Counter
PLLRC
PLL
MUL
PLL
PLL
OUT
LOCK
PLLCK
Figure
179
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