AT91SAM7X128 Atmel, AT91SAM7X128 Datasheet - Page 426

• Manufacturer Part Number: AT91SAM7X128
• Description: MCU 32-Bit 91S ARM7TDMI RISC 128KB Flash 1.8V/3.3V 100-Pin LQFP
• Manufacturer: Atmel

Specifications of AT91SAM7X128

• Package: 100LQFP
• Device Core: ARM7TDMI
• Family Name: 91S
• Maximum Speed: 55 MHz
• Ram Size: 32 KB
• Program Memory Size: 128 KB
• Operating Supply Voltage: 1.8|3.3 V
• Data Bus Width: 32 Bit
• Program Memory Type: Flash
• Number Of Programmable I/os: 62
• Interface Type: CAN/Ethernet/SPI/I2S/TWI/USART/USB
• On-chip Adc: 8-chx10-bit
• Operating Temperature: -40 to 85 °C
• Number Of Timers: 3

33.5.2
33.5.2.1
33.5.2.2
426
AT91SAM7X512/256/128 Preliminary
PWM Channel
Block Diagram
Waveform Properties
After a reset of the PWM controller, DIVA (DIVB) and PREA (PREB) in the PWM Mode register
are set to 0. This implies that after reset clkA (clkB) are turned off.
At reset, all clocks provided by the modulo n counter are turned off except clock “clk”. This situa-
tion is also true when the PWM master clock is turned off through the Power Management
Controller.
Figure 33-3. Functional View of the Channel Block Diagram
Each of the 4 channels is composed of three blocks:
The different properties of output waveforms are:
inputs from
from clock
• A clock selector which selects one of the clocks provided by the clock generator described in
• An internal counter clocked by the output of the clock selector. This internal counter is
• A comparator used to generate events according to the internal counter value. It also
• the internal clock selection. The internal channel counter is clocked by one of the clocks
• the waveform period. This channel parameter is defined in the CPRD field of the
generator
APB bus
inputs
Section 33.5.1 “PWM Clock Generator” on page
incremented or decremented according to the channel configuration and comparators events.
The size of the internal counter is 16 bits.
computes the PWMx output waveform according to the configuration.
provided by the clock generator described in the previous section. This channel parameter is
defined in the CPRE field of the PWM_CMRx register. This field is reset at 0.
PWM_CPRDx register.
- If the waveform is left aligned, then the output waveform period depends on the counter
source clock and can be calculated:
By using the Master Clock (MCK) divided by an X given prescaler value
(with X being 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, or 1024), the resulting period formula
will be:
(
------------------------------- -
X
×
MCK
CPRD
)
Channel
Selector
Clock
Counter
Internal
425.
Comparator
6120H–ATARM–17-Feb-09
PWMx
output waveform