AT91SAM7X128 Atmel, AT91SAM7X128 Datasheet - Page 520

no-image

AT91SAM7X128

Manufacturer Part Number
AT91SAM7X128
Description
MCU 32-Bit 91S ARM7TDMI RISC 128KB Flash 1.8V/3.3V 100-Pin LQFP
Manufacturer
Atmel
Datasheet

Specifications of AT91SAM7X128

Package
100LQFP
Device Core
ARM7TDMI
Family Name
91S
Maximum Speed
55 MHz
Ram Size
32 KB
Program Memory Size
128 KB
Operating Supply Voltage
1.8|3.3 V
Data Bus Width
32 Bit
Program Memory Type
Flash
Number Of Programmable I/os
62
Interface Type
CAN/Ethernet/SPI/I2S/TWI/USART/USB
On-chip Adc
8-chx10-bit
Operating Temperature
-40 to 85 °C
Number Of Timers
3

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AT91SAM7X128-AU
Manufacturer:
ATMEL
Quantity:
1 045
Part Number:
AT91SAM7X128-AU
Manufacturer:
Atmel
Quantity:
10 000
Part Number:
AT91SAM7X128-AU
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
Part Number:
AT91SAM7X128-AU-999
Manufacturer:
Atmel
Quantity:
10 000
Part Number:
AT91SAM7X128-CU
Manufacturer:
Atmel
Quantity:
10 000
Part Number:
AT91SAM7X128-CU
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
Part Number:
AT91SAM7X128-CU-999
Manufacturer:
Atmel
Quantity:
10 000
Part Number:
AT91SAM7X128B-AU
Manufacturer:
Atmel
Quantity:
1 929
Part Number:
AT91SAM7X128B-AU
Manufacturer:
Atmel
Quantity:
10 000
Part Number:
AT91SAM7X128B-AU
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
Figure 36-9. Disabling Low-power Mode
36.7
36.7.1
6120H–ATARM–17-Feb-09
Functional Description
(CAN_MSRx)
CAN Controller Initialization
(CAN_SR)
WAKEUP
(CAN_MR)
(CAN_SR)
CAN BUS
SLEEP
MRDY
LPM
After power-up reset, the CAN controller is disabled. The CAN controller clock must be activated
by the Power Management Controller (PMC) and the CAN controller interrupt line must be
enabled by the interrupt controller (AIC).
The CAN controller must be initialized with the CAN network parameters. The CAN_BR register
defines the sampling point in the bit time period. CAN_BR must be set before the CAN controller
is enabled by setting the CANEN field in the CAN_MR register.
The CAN controller is enabled by setting the CANEN flag in the CAN_MR register. At this stage,
the internal CAN controller state machine is reset, error counters are reset to 0, error flags are
reset to 0.
Once the CAN controller is enabled, bus synchronization is done automatically by scanning
eleven recessive bits. The WAKEUP bit in the CAN_SR register is automatically set to 1 when
the CAN controller is synchronized (WAKEUP and SLEEP are stuck at 0 after a reset).
The CAN controller can start listening to the network in Autobaud Mode. In this case, the error
counters are locked and a mailbox may be configured in Receive Mode. By scanning error flags,
the CAN_BR register values synchronized with the network. Once no error has been detected,
the application disables the Autobaud Mode, clearing the ABM field in the CAN_MR register.
Message lost
Interframe synchronization
Bus Activity Detected
Message x
AT91SAM7X512/256/128 Preliminary
520

Related parts for AT91SAM7X128