AT91SAM7X128 Atmel, AT91SAM7X128 Datasheet - Page 652

• Manufacturer Part Number: AT91SAM7X128
• Description: MCU 32-Bit 91S ARM7TDMI RISC 128KB Flash 1.8V/3.3V 100-Pin LQFP
• Manufacturer: Atmel

Specifications of AT91SAM7X128

• Package: 100LQFP
• Device Core: ARM7TDMI
• Family Name: 91S
• Maximum Speed: 55 MHz
• Ram Size: 32 KB
• Program Memory Size: 128 KB
• Operating Supply Voltage: 1.8|3.3 V
• Data Bus Width: 32 Bit
• Program Memory Type: Flash
• Number Of Programmable I/os: 62
• Interface Type: CAN/Ethernet/SPI/I2S/TWI/USART/USB
• On-chip Adc: 8-chx10-bit
• Operating Temperature: -40 to 85 °C
• Number Of Timers: 3

41.3.2
41.3.2.1
41.3.2.2
41.3.3
41.3.3.1
41.3.4
41.3.4.1
41.3.4.2
652
AT91SAM7X512/256/128 Preliminary
Controller Area Network (CAN)
Embedded Flash Controller (EFC)
Ethernet MAC (EMAC)
CAN: Low Power Mode and Error Frame
CAN: Low Power Mode and Pending Transmit Messages
EFC: Embedded Flash Access Time
EMAC: Possible Event Loss when Reading EMAC_ISR
EMAC: Possible Event Loss when Reading the Statistics Register Block
If the Low Power Mode is activated while the CAN is generating an error frame, this error frame
may be shortened.
None
No pending transmit messages may be sent once the CAN Controller enters Low-power Mode.
Check that all messages have been sent by reading the related Flags before entering Low-
power Mode.
The embedded Flash maximum access time is 25 MHz (instead of 30 MHz at zero Wait State
(FWS = 0). The maximum operating frequency with one Wait State (FWS = 1) is still 55 MHz.
Set one wait state (FWS = 1) if the temperature is above 25 MHz.
If an event occurs within the same clock cycle in which the EMAC_ISR is read, the correspond-
ing bit might be cleared even though it has not been read at 1. This might lead to the loss of this
event.
Each time the software reads EMAC_ISR, it has to check the contents of the Transmit Status
Register (EMAC_TSR), the Receive Status Register (EMAC_RSR) and the Network Status
Register (EMAC_NSR), as the possible lost event is still notified in one of these registers.
If an event occurs within the same clock cycle during which a statistics register is read, the cor-
responding counter might lose this event. This might lead to the loss of the incrementation of
one for this counter.
None
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
6120H–ATARM–17-Feb-09