PEB 4364 T V1.2 Infineon Technologies, PEB 4364 T V1.2 Datasheet - Page 122

• Manufacturer Part Number: PEB 4364 T V1.2
• Description: IC SLIC VOICE ACCESS PDSO-36
• Manufacturer: Infineon Technologies
• Series: DuSLICr

Specifications of PEB 4364 T V1.2

• Function: Dual Channel Subscriber Line Interface Circuit (DuSLIC)
• Interface: IOM-2, PCM
• Number Of Circuits: 2
• Voltage - Supply: 3.3 V ~ 5 V
• Current - Supply: 105mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 36-PDSO
• Includes: DTMF Generator and Decoder, Line Echo Cancellation (LEC), Teletax (TTX) Generation, Universal Tone Detection (UTD)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power (watts): -
• Other names: PEB4364TV1.2XT; SP000007728

4
The DuSLIC offers two different interfaces to connect to a digital network:
•
•
The PCM/IOM-2 pin selects the interface mode.
– PCM/IOM-2 = 0: IOM-2 mode.
– PCM/IOM-2 = 1: PCM/ C mode.
The analog TIP/RING Interface connects the DuSLIC to the subscriber.
4.1
In PCM/ C Interface mode, voice and control data are separated and handled by
different pins of the SLICOFI-2x. Voice data are transferred via the PCM highways while
control data are transferred using the Microcontroller Interface.
4.1.1
The serial PCM Interface is used to transfer A-Law or -Law-compressed voice data. In
test mode, the PCM Interface can also transfer linear data. The eight signals of the PCM
Interface are used as follows (two PCM highways):
PCLK:
FSC:
DRA:
DRB:
DXA:
DXB:
TCA:
TCB:
The FSC pulse identifies the beginning of a receive and transmit frame for both channels
(see
(DXB) and DRA (DRB) lines. On all channels, bytes are serialized with the MSB first. As
a default setting, the rising edge indicates the start of the bit, while the falling edge is
used to buffer the contents of the received data on DRA (DRB). If double clock rate is
selected (PCLK clock rate is twice the data rate), the first rising edge indicates the start
of a bit, while, by default, the second falling edge is used to buffer the contents of the
data line DRA (DRB).
Preliminary Data Sheet
PCM Interface combined with a serial microcontroller interface
IOM-2 Interface.
Figure
PCM Clock, 128 kHz to 8192 kHz
Frame Synchronization Clock, 8 kHz
Receive Data Input for PCM Highway A
Receive Data Input for PCM Highway B
Transmit Data Output for PCM Highway A
Transmit Data Output for PCM Highway B
Transmit Control Output for PCM Highway A. Active low during transmission
Transmit Control Output for PCM Highway B. Active low during transmission
Interfaces
PCM Interface with a Serial Microcontroller Interface
PCM Interface
52). The PCLK clock signal synchronizes the data transfer on the DXA
122
DS3, 2003-07-11
Interfaces
DuSLIC