PEB 4364 T V1.2 Infineon Technologies, PEB 4364 T V1.2 Datasheet - Page 336

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PEB 4364 T V1.2

Manufacturer Part Number
PEB 4364 T V1.2
Description
IC SLIC VOICE ACCESS PDSO-36
Manufacturer
Infineon Technologies
Series
DuSLICr
Datasheet

Specifications of PEB 4364 T V1.2

Function
Dual Channel Subscriber Line Interface Circuit (DuSLIC)
Interface
IOM-2, PCM
Number Of Circuits
2
Voltage - Supply
3.3 V ~ 5 V
Current - Supply
105mA
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
36-PDSO
Includes
DTMF Generator and Decoder, Line Echo Cancellation (LEC), Teletax (TTX) Generation, Universal Tone Detection (UTD)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Power (watts)
-
Other names
PEB4364TV1.2XT
SP000007728
6.1.3
Minimum delays occur when both Frequency Response Receive and Transmit filters (bit
FRR-DIS and bit FRX-DIS in register BCR4 set to 1) are disabled. That includes the
delay through A/D and D/A converters. Specific filter programming may cause additional
group delays. Absolute Group delay also depends on the programmed time slot.
Group delay distortion stays within the limits in the figures below.
Table 77
Parameter
Transmit delay
Receive delay
Figure 77
Signal level 0 dBm0
6.1.4
With a 0 dBm0 sine wave with a frequency of
input, the level of any resulting out-of-band signal at the analog output will stay at least
X dB below a 0 dBm0, 1 kHz sine wave reference signal at the analog output.
Preliminary Data Sheet
400
300
200
150
100
500
0
Group Delay
Out-of-Band Signals at Analog Output (Receive)
0
Group Delay Absolute Values: Signal level 0 dBm0
Group Delay Distortion Receive and Transmit
Symbol
D
D
0.5 0.6
XA
RA
min.
400
290
1
Limit Values
typ.
490
380
1.5
336
max.
585
475
2
f
(300 Hz to 3.4 kHz) applied to the digital
Unit
Frequency
s
s
2.6
2.8 3
Test Condition
f
f
Electrical Characteristics
= 1.5 kHz
= 1.5 kHz
3.5
DS3, 2003-07-11
ezm00112
kHz
4
DuSLIC
Fig.

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