PEB 4364 T V1.2 Infineon Technologies, PEB 4364 T V1.2 Datasheet - Page 62

• Manufacturer Part Number: PEB 4364 T V1.2
• Description: IC SLIC VOICE ACCESS PDSO-36
• Manufacturer: Infineon Technologies
• Series: DuSLICr

Specifications of PEB 4364 T V1.2

• Function: Dual Channel Subscriber Line Interface Circuit (DuSLIC)
• Interface: IOM-2, PCM
• Number Of Circuits: 2
• Voltage - Supply: 3.3 V ~ 5 V
• Current - Supply: 105mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 36-PDSO
• Includes: DTMF Generator and Decoder, Line Echo Cancellation (LEC), Teletax (TTX) Generation, Universal Tone Detection (UTD)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power (watts): -
• Other names: PEB4364TV1.2XT; SP000007728

5. If this bit is set, write at least BRS + 2 bytes (see POP register CIS-BRS) of Caller ID
6. Wait for the next interrupt and check again the CIS-REQ bit.
7. If this bit is set, send the next data to the Caller ID-data buffer but not more than (48
8. Repeat steps 6 and 7 as long as there is data to be sent.
9. Immediately after sending the last Caller ID data bit to the Caller ID sender buffer, set
The end of the CID transmission can also be controlled by not setting CIS-AUTO and
leaving CIS-EN at 1. If the Caller ID buffer becomes empty, an interrupt is generated to
indicate buffer underflow (CIS-BUF). If CIS-BUF is set, reset CIS-EN to 0 with at least 1
ms delay, in order to allow to send the last bit of Caller ID data.
In case of errors in the handling of the CID data buffer, CIS-BUF (buffer underflow) and
CIS-BOF (buffer overflow) indicate these errors. CID transmission should be stopped in
any of these cases as unpredictable results may occur.
Note: CID data will be sent out with the LSB first
If CIS-FRM is set to 1: seizure and mark bits are generated automatically (according to
the settings of CIS-SEIZ-H/L and CIS-MARK-H/L) as well as start and stop bits for every
byte.
Preliminary Data Sheet
data but not more than 48 bytes to the Caller ID sender buffer register CIS-DAT.
– BRS) bytes. CIS-REQ bit gets reset to 0, if the data buffer is filled again above the
Caller ID sender buffer request size (BRS).
the bit CIS-AUTO to 1 and subsequently, after a time delay of at least 500 µs, the bit
CIS-EN to 0. After processing the last bit, the Caller ID sender will stop automatically
and reset the CIS-ACT bit in register INTREG4 to 0. No more CIS interrupts will be
generated until the Caller ID sender is enabled again (interrupt bits: CIS-BOF, CIS-
BUF and CIS-REQ).
62
Functional Description
DS3, 2003-07-11
DuSLIC