PEB 4364 T V1.2 Infineon Technologies, PEB 4364 T V1.2 Datasheet - Page 124

• Manufacturer Part Number: PEB 4364 T V1.2
• Description: IC SLIC VOICE ACCESS PDSO-36
• Manufacturer: Infineon Technologies
• Series: DuSLICr

Specifications of PEB 4364 T V1.2

• Function: Dual Channel Subscriber Line Interface Circuit (DuSLIC)
• Interface: IOM-2, PCM
• Number Of Circuits: 2
• Voltage - Supply: 3.3 V ~ 5 V
• Current - Supply: 105mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 36-PDSO
• Includes: DTMF Generator and Decoder, Line Echo Cancellation (LEC), Teletax (TTX) Generation, Universal Tone Detection (UTD)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power (watts): -
• Other names: PEB4364TV1.2XT; SP000007728

When DuSLIC is transmitting data on DXA (DXB), pin TCA (TCB) is activated to control
an external driving device.
The DRA/B and DXA/B pins may be connected to form a bidirectional data pin for special
purposes, such as for the Serial Interface Port (SIP) with the Subscriber Line Data (SLD)
bus. The SLD approach provides a common interface for analog or digital per-line
components. For more details, please see the
available on request from Infineon Technologies.
Table 28
1536 kHz).
Table 28
Clock Rate PCLK
[kHz]
128
256
256
512
512
768
768
1024
1024
2048
2048
4096
4096
8192
8192
f
f
1) Ordering No. B115-H6377-X-X-7600, published by Infineon Technologies.
Preliminary Data Sheet
Valid PCLK clock rates are:
shows PCM Interface examples; other frequencies are also possible (such as
SLICOFI-2x PCM Interface Configuration
Single/Double
Clock [1/2]
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
1
2
f
= n
64 kHz (2 n 128)
Time Slots
[per highway]
2
2
4
4
8
6
12
8
16
16
32
32
64
64
128
f/64
f/128
124
ICs for Communications
Data Rate
[kbit/s per highway]
128
128
256
256
512
384
768
512
1024
1024
2048
2048
4096
4096
8192
f
f/2
1)
DS3, 2003-07-11
User’s Manual
Interfaces
DuSLIC