PEB 4364 T V1.2 Infineon Technologies, PEB 4364 T V1.2 Datasheet - Page 276

• Manufacturer Part Number: PEB 4364 T V1.2
• Description: IC SLIC VOICE ACCESS PDSO-36
• Manufacturer: Infineon Technologies
• Series: DuSLICr

Specifications of PEB 4364 T V1.2

• Function: Dual Channel Subscriber Line Interface Circuit (DuSLIC)
• Interface: IOM-2, PCM
• Number Of Circuits: 2
• Voltage - Supply: 3.3 V ~ 5 V
• Current - Supply: 105mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 36-PDSO
• Includes: DTMF Generator and Decoder, Line Echo Cancellation (LEC), Teletax (TTX) Generation, Universal Tone Detection (UTD)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power (watts): -
• Other names: PEB4364TV1.2XT; SP000007728

Bit
After a hardware reset, the RSTAT bit is set and generates an interrupt. Therefore, the
default value of INTREG2 is 20
value changes to 4F
READY
RSTAT
IO[4:1]-DU
Bit
Bit
Preliminary Data Sheet
08
09
0A
H
H
H
INTREG2
INTREG3
INTREG4
7
0
7
0
7
0
Data on I/O pins 1 to 4 filtered by the DUP-IO counter and interrupt
generation masked by the IO[4:1]-DU-M bits. A change of any of these
bits generates an interrupt.
Reset status since last interrupt.
RSTAT = 0
RSTAT = 1
Indicates whether ramp generator has finished. An interrupt is only
generated if the READY bit changes from 0 to 1. At a new start of the
ramp generator, the bit is set to 0. For further information regarding soft
reversal see
READY = 0
READY = 1
READY RSTAT
H
.
6
6
0
6
0
Interrupt Register 2 (read-only)
Interrupt Register 3 (read-only)
Interrupt Register 4 (read-only)
Chapter
Ramp generator active.
Ramp generator not active.
No reset has occurred since the last interrupt.
Reset has occurred since the last interrupt.
H
5
5
0
5
0
. After reading all four interrupt registers, the INTREG2
2.7.2.1.
4
0
4
0
4
0
276
3
3
0
3
0
2
IO[4:1]-DU
2
0
2
0
20
00
00
H
H
H
1
1
0
1
0
DS3, 2003-07-11
DuSLIC
0
0
0
0
0
Y
Y
Y