PEB 4364 T V1.2 Infineon Technologies, PEB 4364 T V1.2 Datasheet - Page 60

• Manufacturer Part Number: PEB 4364 T V1.2
• Description: IC SLIC VOICE ACCESS PDSO-36
• Manufacturer: Infineon Technologies
• Series: DuSLICr

Specifications of PEB 4364 T V1.2

• Function: Dual Channel Subscriber Line Interface Circuit (DuSLIC)
• Interface: IOM-2, PCM
• Number Of Circuits: 2
• Voltage - Supply: 3.3 V ~ 5 V
• Current - Supply: 105mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 36-PDSO
• Includes: DTMF Generator and Decoder, Line Echo Cancellation (LEC), Teletax (TTX) Generation, Universal Tone Detection (UTD)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power (watts): -
• Other names: PEB4364TV1.2XT; SP000007728

DuSLIC-E/-E2/-P FSK Generation
Different countries use different standards to send Caller ID information.
The DuSLIC-E/-E2/-P chip set is compatible with the widely used Bellcore GR-30-
CORE, British Telecom (BT) SIN227, SIN242, and the UK Cable Communications
Association (CCA) specification TW/P&E/312 standards. Continuous phase binary
Frequency Shift Keying (FSK) modulation is used for coding that is compatible with
BELL 202 (see
can be easily adapted to these requirements by programming via the microcontroller
interface. Coefficient sets are provided for the most common standards.
Table 7
Characteristic
Mark (Logic 1)
Space (Logic 0)
Modulation
Transmission rate
Data format
The Caller ID data of the calling party can be transferred via the microcontroller interface
into a SLICOFI-2 buffer register. The SLICOFI-2 will start sending the FSK signal when
the CIS-EN bit is set and the CID-data buffer is filled up to CIS-BRS plus 1 byte. The data
transfer into the buffer register is handled by a SLICOFI-2 interrupt signal. Caller data is
transferred from the buffer via the interface pins to the SLIC-E/-E2/-P and is fed to the
Tip and Ring wires. The Caller ID data bytes from the CID-data buffer are sent with the
Least Significant Bit (LSB) first.
DuSLIC-E/-E2/-P offers two different levels of framing:
•
•
The example below shows the signaling of a CID on-hook data transmission in
accordance with Bellcore specifications. The Caller ID information applied on Tip and
Ring is sent during the period between the first and second ring burst.
Preliminary Data Sheet
A basic low-level framing mode
A high-level framing mode
All the data necessary to implement the FSK data stream—including channel
seizure, mark sequence, and framing for the data packet or checksum—must be
configured by firmware. SLICOFI-2 transmits the data stream in the same order in
which the data is written to the buffer register.
The number of channel seizure and mark bits can be programmed and are
automatically sent by the DuSLIC-E/-E2/-P. Only the data packet information must
be written into the CID buffer. Start and stop bits are automatically inserted by the
SLICOFI-2.
FSK Modulation Characteristics
Table
7) and ITU-T V.23, the most common standards. The SLICOFI-2
ITU-T V.23
1300 ± 3 Hz
2100 ± 3 Hz
60
Serial binary asynchronous
1200 ± 6 baud
FSK
Bell 202
1200 ± 3 Hz
2200 ± 3 Hz
Functional Description
DS3, 2003-07-11
DuSLIC