PEB 4364 T V1.2 Infineon Technologies, PEB 4364 T V1.2 Datasheet - Page 272

• Manufacturer Part Number: PEB 4364 T V1.2
• Description: IC SLIC VOICE ACCESS PDSO-36
• Manufacturer: Infineon Technologies
• Series: DuSLICr

Specifications of PEB 4364 T V1.2

• Function: Dual Channel Subscriber Line Interface Circuit (DuSLIC)
• Interface: IOM-2, PCM
• Number Of Circuits: 2
• Voltage - Supply: 3.3 V ~ 5 V
• Current - Supply: 105mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 36-PDSO
• Includes: DTMF Generator and Decoder, Line Echo Cancellation (LEC), Teletax (TTX) Generation, Universal Tone Detection (UTD)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power (watts): -
• Other names: PEB4364TV1.2XT; SP000007728

Bit
DBL-CLK
X-SLOPE
R-SLOPE
NO-
DRIVE-0
SHIFT
PCMO[2:0] All PCM timing is moved by PCMO data periods against the FSC signal.
Preliminary Data Sheet
05
H
DBL-CLK X-SLOPE R-SLOPE NO-DRIVE-0
PCMC1
7
Clock mode for the PCM interface (see
DBL-CLK = 0
DBL-CLK = 1
Transmit Slope (see
X-SLOPE = 0
X-SLOPE = 1
Receive Slope (see
R-SLOPE = 0
R-SLOPE = 1
Driving Mode for Bit 0 (only available in single-clocking mode).
NO-DRIVE = 0
NO-DRIVE = 1
Shifts the access edges by one clock cycle in double clocking mode.
SHIFT = 0
SHIFT = 1
PCMO[2:0] = 0 0 0
PCMO[2:0] = 0 0 1
PCMO[2:0] = 1 1 1
6
PCM Configuration Register 1
5
Figure 53
Figure 53
Single clocking is used.
Double clocking is used.
Transmission starts with rising edge of the clock.
Transmission starts with falling edge of the clock.
Data is sampled with falling edge of the clock.
Data is sampled with rising edge of the clock.
No shift takes place.
Shift takes place.
Bit 0 is driven the entire clock period.
Bit 0 is driven during the first half of the clock period
only.
No offset is added.
One data period is added.
Seven data periods are added.
272
on
on
4
Page
Page
Figure 53
125).
125).
SHIFT
3
on
00
Page
2
H
PCMO[2:0]
DS3, 2003-07-11
125).
1
DuSLIC
N
0