AT90CAN128-16AE ATMEL Corporation, AT90CAN128-16AE Datasheet - Page 111

• Manufacturer Part Number: AT90CAN128-16AE
• Description: 8-bit Avr Microcontroller With 128K Bytes of Isp Flash And CAN Controller.flash (Kbytes) 128 Vcc (V) 2.7-5.5 EEPROM (Kbytes) 4 SRAM (bytes) 4K CAN (mess. Obj.) 15
• Manufacturer: ATMEL Corporation

Definitions
Compatibility
4250C–CAN–03/04
inactive when no clock source is selected. The output from the Clock Select logic is
referred to as the timer clock (clk
The double buffered Output Compare Registers (OCRnx) are compared with the
Timer/Counter value at all time. The result of the compare can be used by the Waveform
Generator to generate a PWM or variable frequency output on the Output Compare pin
(OCnx). See “Output Compare Units” on page 119 . The compare match event will also
set the Compare Match Flag (OCFnx) which can be used to generate an Output Com-
pare interrupt request.
The Input Capture Register can capture the Timer/Counter value at a given external
(edge triggered) event on either the Input Capture pin (ICPn) or on the Analog Compar-
ator pins (See “Analog Comparator” on page 260 ) The Input Capture unit includes a
digital filtering unit (Noise Canceler) for reducing the chance of capturing noise spikes.
The TOP value, or maximum Timer/Counter value, can in some modes of operation be
defined by either the OCRnA Register, the ICRn Register, or by a set of fixed values.
When using OCRnA as TOP value in a PWM mode, the OCRnA Register can not be
used for generating a PWM output. However, the TOP value will in this case be double
buffered allowing the TOP value to be changed in run time. If a fixed TOP value is
required, the ICRn Register can be used as an alternative, freeing the OCRnA to be
used as PWM output.
The following definitions are used extensively throughout the section:
Table 59. Definitions
The 16-bit Timer/Counter has been updated and improved from previous versions of the
16-bit AVR Timer/Counter. This 16-bit Timer/Counter is fully compatible with the earlier
version regarding:
•
•
•
The following control bits have changed name, but have same functionality and register
location:
•
•
•
The following registers are added to the 16-bit Timer/Counter:
•
•
BOTTOM
MAX
TOP
All 16-bit Timer/Counter related I/O Register address locations, including Timer
Interrupt Registers.
Bit locations inside all 16-bit Timer/Counter Registers, including Timer Interrupt
Registers.
Interrupt Vectors.
PWMn0 is changed to WGMn0.
PWMn1 is changed to WGMn1.
CTCn is changed to WGMn2.
Timer/Counter Control Register C (TCCRnC).
Output Compare Register C, OCRnCH and OCRnCL, combined OCRnC.
The counter reaches the BOTTOM when it becomes 0x0000.
The counter reaches its MAXimum when it becomes 0xFFFF (decimal 65,535).
The counter reaches the TOP when it becomes equal to the highest value in the
count sequence. The TOP value can be assigned to be one of the fixed values:
0x00FF, 0x01FF, or 0x03FF, or to the value stored in the OCR
ter. The assignment is dependent of the mode of operation.
T
n
).
AT90CAN128
n
A or ICR
n
Regis-
111