AT90CAN128-16AE ATMEL Corporation, AT90CAN128-16AE Datasheet - Page 20

• Manufacturer Part Number: AT90CAN128-16AE
• Description: 8-bit Avr Microcontroller With 128K Bytes of Isp Flash And CAN Controller.flash (Kbytes) 128 Vcc (V) 2.7-5.5 EEPROM (Kbytes) 4 SRAM (bytes) 4K CAN (mess. Obj.) 15
• Manufacturer: ATMEL Corporation

EEPROM Data Memory
EEPROM Read/Write Access
The EEPROM Address
Registers – EEARH and
EEARL
The EEPROM Data Register –
EEDR
20
AT90CAN128
The AT90CAN128 contains 4-Kbytes of data EEPROM memory. It is organized as a
separate data space, in which single bytes can be read and written. The EEPROM has
an endurance of at least 100,000 write/erase cycles. The access between the EEPROM
and the CPU is described in the following, specifying the EEPROM Address Registers,
the EEPROM Data Register, and the EEPROM Control Register.
For a detailed description of SPI, JTAG and Parallel data downloading to the EEPROM,
see “SPI Serial Programming Overview” on page 335, “JTAG Programming Overview”
on page 340, and “Parallel Programming Overview” on page 327 respectively.
The EEPROM Access Registers are accessible in the I/O space.
The write access time for the EEPROM is given in Table 1. A self-timing function, how-
ever, lets the user software detect when the next byte can be written. If the user code
contains instructions that write the EEPROM, some precautions must be taken. In
heavily filtered power supplies, V
causes the device for some period of time to run at a voltage lower than specified as
minimum for the clock frequency used. See “Preventing EEPROM Corruption” on page
24 for details on how to avoid problems in these situations.
In order to prevent unintentional EEPROM writes, a specific write procedure must be fol-
lowed. Refer to the description of the EEPROM Control Register for details on this.
When the EEPROM is read, the CPU is halted for four clock cycles before the next
instruction is executed. When the EEPROM is written, the CPU is halted for two clock
cycles before the next instruction is executed.
• Bits 15..12 – Reserved Bits
These bits are reserved bits in the AT90CAN128 and will always read as zero.
• Bits 11..0 – EEAR11..0: EEPROM Address
The EEPROM Address Registers – EEARH and EEARL specify the EEPROM address
in the 4-Kbytes EEPROM space. The EEPROM data bytes are addressed linearly
between 0 and 4,095. The initial value of EEAR is undefined. A proper value must be
written before the EEPROM may be accessed.
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
EEAR7
EEDR7
R/W
R/W
15
–
7
R
0
X
7
0
EEAR6
EEDR6
R/W
R/W
14
R
X
–
6
0
6
0
EEAR5
EEDR5
R/W
R/W
13
–
5
R
0
X
5
0
CC
is likely to rise or fall slowly on power-up/down. This
EEAR4
EEDR4
R/W
R/W
12
R
X
–
4
0
4
0
EEAR11
EEAR3
EEDR3
R/W
R/W
R/W
11
X
X
3
3
0
EEAR10
EEDR2
EEAR2
R/W
R/W
R/W
10
2
0
X
X
2
EEDR1
EEAR9
EEAR1
R/W
R/W
R/W
1
0
X
X
9
1
EEDR0
EEAR8
EEAR0
R/W
R/W
R/W
0
0
X
X
4250C–CAN–03/04
8
0
EEARH
EEDR
EEARL