AT90CAN128-16AE ATMEL Corporation, AT90CAN128-16AE Datasheet - Page 378

• Manufacturer Part Number: AT90CAN128-16AE
• Description: 8-bit Avr Microcontroller With 128K Bytes of Isp Flash And CAN Controller.flash (Kbytes) 128 Vcc (V) 2.7-5.5 EEPROM (Kbytes) 4 SRAM (bytes) 4K CAN (mess. Obj.) 15
• Manufacturer: ATMEL Corporation

378
Mnemonics
MOVW
SWAP
ELPM
ELPM
ELPM
BSET
BCLR
BRIE
BRID
MOV
ROL
ROR
ASR
SEC
SEN
SEH
LPM
LPM
LPM
SPM
LSR
BST
BLD
CLC
CLN
SEZ
CLZ
SES
CLS
SEV
CLV
SET
CLT
CLH
LDD
LDD
LDS
STD
STD
STS
CBI
LSL
SBI
SEI
CLI
LDI
LD
LD
LD
LD
LD
LD
LD
LD
LD
ST
ST
ST
ST
ST
ST
ST
ST
ST
AT90CAN128
Operands
Rd, Z+q
Rd,Y+q
Rd, X+
Rd, - X
Rd, Y+
Rd, - Y
Rd, Z+
Y+q,Rr
Z+q,Rr
Rd, Z+
Rd, Z+
Rd, Rr
Rd, Rr
X+, Rr
- X, Rr
Y+, Rr
- Y, Rr
Rd, -Z
Z+, Rr
Rd, K
Rd, X
Rd, Y
Rd, Z
-Z, Rr
Rd, Z
Rd, Z
Rd, b
Rd, k
X, Rr
Y, Rr
Rr, b
Z, Rr
k, Rr
P,b
P,b
Rd
Rd
Rd
Rd
Rd
Rd
s
s
k
k
BIT AND BIT-TEST INSTRUCTIONS
DATA TRANSFER INSTRUCTIONS
Extended Load Program Memory and Post-Inc
Load Program Memory and Post-Inc
Clear Twos Complement Overflow
Set Twos Complement Overflow.
Extended Load Program Memory
Extended Load Program Memory
Store Indirect with Displacement
Store Indirect with Displacement
Load Indirect with Displacement
Load Indirect with Displacement
Clear Half Carry Flag in SREG
Set Half Carry Flag in SREG
Rotate Right Through Carry
Branch if Interrupt Disabled
Bit Store from Register to T
Store Indirect and Post-Inc.
Store Indirect and Pre-Dec.
Store Indirect and Post-Inc.
Store Indirect and Pre-Dec.
Store Indirect and Post-Inc.
Store Indirect and Pre-Dec.
Branch if Interrupt Enabled
Load Indirect and Post-Inc.
Load Indirect and Pre-Dec.
Load Indirect and Post-Inc.
Load Indirect and Pre-Dec.
Load Indirect and Post-Inc.
Load Indirect and Pre-Dec.
Rotate Left Through Carry
Bit load from T to Register
Move Between Registers
Load Direct from SRAM
Clear Bit in I/O Register
Global Interrupt Enable
Global Interrupt Disable
Store Program Memory
Clear Signed Test Flag
Load Program Memory
Load Program Memory
Set Bit in I/O Register
Store Direct to SRAM
Arithmetic Shift Right
Set Signed Test Flag
Copy Register Word
Clear Negative Flag
Logical Shift Right
Set Negative Flag
Logical Shift Left
Clear T in SREG
Load Immediate
Clear Zero Flag
Description
Set T in SREG
Swap Nibbles
Set Zero Flag
Store Indirect
Store Indirect
Store Indirect
Load Indirect
Load Indirect
Load Indirect
Clear Carry
Flag Clear
Set Carry
Flag Set
Rd
Rd(3..0) Rd(7..4),Rd(7..4) Rd(3..0)
Rd(0) C,Rd(n+1)
Rd(7) C,Rd(n)
(RAMPZ:Z), RAMPZ:Z
if ( I = 1) then PC
if ( I = 0) then PC
Rd(n+1)
Rd(n)
Rd(n)
Rd
Rd
Rd+1:Rd
X
Y
(X)
(Y)
Z
(Z)
X
Y
Z
Rd
Rd
R0
Rd
SREG(s)
SREG(s)
Rd
Rd
Operation
I/O(P,b)
I/O(P,b)
(Y + q)
(Z + q)
(Z)
Rd(n+1), Rd(7)
Rd(b)
X - 1, Rd
Y - 1, Rd
Z - 1, Rd
T
X - 1, (X)
Y - 1, (Y)
Z - 1, (Z)
Rd
Rd
Rd
Rd
R0
Rd
Rd
Rd
(X)
(Y)
(Z)
(k)
(X), X
(Y), Y
Rr, X
Rr, Y
Rr, Z
Rd(n+1), n=0..6
C
C
N
N
S
S
V
V
H
H
(Z), Z
(Z), Z
Rd(n), Rd(0)
Z
Z
T
T
I
I
(RAMPZ:Z)
(RAMPZ:Z)
(Z + q)
Rr(b)
(Y + q)
Rd(n+1),C Rd(0)
R1:R0
1
0
(X)
(Y)
(Z)
(Z)
(Z)
1
0
1
0
1
0
1
0
1
0
1
0
1
0
Rr
Rr
Rr
(k)
Rr
Rr
Rr+1:Rr
Rd(n),C Rd(7)
K
T
Rr
Rr
PC + k + 1
PC + k + 1
1
0
X + 1
Y + 1
Z + 1
X + 1
Y + 1
1
0
Z+1
Z+1
(X)
(Y)
(Z)
Rr
Rr
Rr
RAMPZ:Z+1
0
0
SREG(s)
SREG(s)
Z,C,N,V
Z,C,N,V
Z,C,N,V
Z,C,N,V
Z,C,N,V
Flags
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
C
C
N
N
H
H
T
Z
Z
S
S
V
V
T
T
I
I
4250C–CAN–03/04
#Clocks
1/2
1/2
2
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
3
3
3
3
3
3
-