AT90CAN128-16AE ATMEL Corporation, AT90CAN128-16AE Datasheet - Page 267

• Manufacturer Part Number: AT90CAN128-16AE
• Description: 8-bit Avr Microcontroller With 128K Bytes of Isp Flash And CAN Controller.flash (Kbytes) 128 Vcc (V) 2.7-5.5 EEPROM (Kbytes) 4 SRAM (bytes) 4K CAN (mess. Obj.) 15
• Manufacturer: ATMEL Corporation

4250C–CAN–03/04
When initiating a single ended conversion by setting the ADSC bit in ADCSRA, the con-
version starts at the following rising edge of the ADC clock cycle. See “Differential
Channels” on page 268 for details on differential conversion timing.
A normal conversion takes 13 ADC clock cycles. The first conversion after the ADC is
switched on (ADEN in ADCSRA is set) takes 25 ADC clock cycles in order to initialize
the analog circuitry.
The actual sample-and-hold takes place 1.5 ADC clock cycles after the start of a normal
conversion and 13.5 ADC clock cycles after the start of an first conversion. When a con-
version is complete, the result is written to the ADC Data Registers, and ADIF is set. In
Single Conversion mode, ADSC is cleared simultaneously. The software may then set
ADSC again, and a new conversion will be initiated on the first rising ADC clock edge.
When Auto Triggering is used, the prescaler is reset when the trigger event occurs. This
assures a fixed delay from the trigger event to the start of conversion. In this mode, the
sample-and-hold takes place two ADC clock cycles after the rising edge on the trigger
source signal. Three additional CPU clock cycles are used for synchronization logic.
In Free Running mode, a new conversion will be started immediately after the conver-
sion completes, while ADSC remains high. For a summary of conversion times, see
Table 98.
Figure 127. ADC Timing Diagram, First Conversion (Single Conversion Mode)
Figure 128. ADC Timing Diagram, Single Conversion
Cycle Number
ADC Clock
ADSC
ADIF
ADCH
ADCL
Cycle Number
ADC Clock
ADEN
ADSC
ADIF
ADCH
ADCL
1
1
2
2
MUX and REFS
Update
MUX and REFS
Update
3
Sample & Hold
12
4
13
5
14
6
15
7
One Conversion
Sample & Hold
16
8
First Conversion
17
9
10
18
Conversion
Complete
11
19
12
20
13
21
22
Sign and MSB of Result
Conversion
Complete
LSB of Result
AT90CAN128
Next Conversion
1
23
2
24
MUX and REFS
Update
3
25
Sign and MSB of Result
Next
Conversion
1
LSB of Result
2
and REFS
Update
MUX
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