AT90CAN128-16AE ATMEL Corporation, AT90CAN128-16AE Datasheet - Page 73

• Manufacturer Part Number: AT90CAN128-16AE
• Description: 8-bit Avr Microcontroller With 128K Bytes of Isp Flash And CAN Controller.flash (Kbytes) 128 Vcc (V) 2.7-5.5 EEPROM (Kbytes) 4 SRAM (bytes) 4K CAN (mess. Obj.) 15
• Manufacturer: ATMEL Corporation

AT90CAN128
(DDB7 set “one”) to serve this function. The OC1C pin is also the output pin for the
PWM mode timer function.
• OC1B, Bit 6
OC1B, Output Compare Match B output. The PB6 pin can serve as an external output
for the Timer/Counter1 Output Compare B. The pin has to be configured as an output
(DDB6 set “one”) to serve this function. The OC1B pin is also the output pin for the PWM
mode timer function.
• OC1A, Bit 5
OC1A, Output Compare Match A output. The PB5 pin can serve as an external output
for the Timer/Counter1 Output Compare A. The pin has to be configured as an output
(DDB5 set “one”) to serve this function. The OC1A pin is also the output pin for the PWM
mode timer function.
• OC2A, Bit 4
OC2A, Output Compare Match A output. The PB4 pin can serve as an external output
for the Timer/Counter2 Output Compare A. The pin has to be configured as an output
(DDB4 set “one”) to serve this function. The OC2A pin is also the output pin for the PWM
mode timer function.
• MISO – Port B, Bit 3
MISO, Master Data input, Slave Data output pin for SPI channel. When the SPI is
enabled as a master, this pin is configured as an input regardless of the setting of
DDB3. When the SPI is enabled as a slave, the data direction of this pin is controlled by
DDB3. When the pin is forced to be an input, the pull-up can still be controlled by the
PORTB3 bit.
• MOSI – Port B, Bit 2
MOSI, SPI Master Data output, Slave Data input for SPI channel. When the SPI is
enabled as a slave, this pin is configured as an input regardless of the setting of DDB2.
When the SPI is enabled as a master, the data direction of this pin is controlled by
DDB2. When the pin is forced to be an input, the pull-up can still be controlled by the
PORTB2 bit.
• SCK – Port B, Bit 1
SCK, Master Clock output, Slave Clock input pin for SPI channel. When the SPI is
enabled as a slave, this pin is configured as an input regardless of the setting of DDB1.
When the SPI is enabled as a master, the data direction of this pin is controlled by
DDB1. When the pin is forced to be an input, the pull-up can still be controlled by the
PORTB1 bit.
• SS – Port B, Bit 0
SS, Slave Port Select input. When the SPI is enabled as a slave, this pin is configured
as an input regardless of the setting of DDB0. As a slave, the SPI is activated when this
pin is driven low. When the SPI is enabled as a master, the data direction of this pin is
controlled by DDB0. When the pin is forced to be an input, the pull-up can still be con-
trolled by the PORTB0 bit.
Table 33 and Table 34 relate the alternate functions of Port B to the overriding signals
shown in Figure 33 on page 68. SPI MSTR INPUT and SPI SLAVE OUTPUT constitute
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