AT90CAN128-16AE ATMEL Corporation, AT90CAN128-16AE Datasheet - Page 314

• Manufacturer Part Number: AT90CAN128-16AE
• Description: 8-bit Avr Microcontroller With 128K Bytes of Isp Flash And CAN Controller.flash (Kbytes) 128 Vcc (V) 2.7-5.5 EEPROM (Kbytes) 4 SRAM (bytes) 4K CAN (mess. Obj.) 15
• Manufacturer: ATMEL Corporation

Store Program Memory
Control and Status Register –
SPMCSR
314
AT90CAN128
point to the Boot Loader Reset and the fuse can only be changed through the serial or
parallel programming interface.
Table 116. Boot Reset Fuse
Note:
The Store Program Memory Control and Status Register contains the control bits
needed to control the Boot Loader operations.
• Bit 7 – SPMIE: SPM Interrupt Enable
When the SPMIE bit is written to one, and the I-bit in the Status Register is set (one), the
SPM ready interrupt will be enabled. The SPM ready Interrupt will be executed as long
as the SPMEN bit in the SPMCSR Register is cleared.
• Bit 6 – RWWSB: Read-While-Write Section Busy
When a Self-Programming (Page Erase or Page Write) operation to the RWW section is
initiated, the RWWSB will be set (one) by hardware. When the RWWSB bit is set, the
RWW section cannot be accessed. The RWWSB bit will be cleared if the RWWSRE bit
is written to one after a Self-Programming operation is completed. Alternatively the
RWWSB bit will automatically be cleared if a page load operation is initiated.
• Bit 5 – Res: Reserved Bit
This bit is a reserved bit in the AT90CAN128 and always read as zero.
• Bit 4 – RWWSRE: Read-While-Write Section Read Enable
When programming (Page Erase or Page Write) to the RWW section, the RWW section
is blocked for reading (the RWWSB will be set by hardware). To re-enable the RWW
section, the user software must wait until the programming is completed (SPMEN will be
cleared). Then, if the RWWSRE bit is written to one at the same time as SPMEN, the
next SPM instruction within four clock cycles re-enables the RWW section. The RWW
section cannot be re-enabled while the Flash is busy with a Page Erase or a Page Write
(SPMEN is set). If the RWWSRE bit is written while the Flash is being loaded, the Flash
load operation will abort and the data loaded will be lost.
• Bit 3 – BLBSET: Boot Lock Bit Set
If this bit is written to one at the same time as SPMEN, the next SPM instruction within
four clock cycles sets Boot Lock bits, according to the data in R0. The data in R1 and
the address in the Z-pointer/RAMPZ are ignored. The BLBSET bit will automatically be
cleared upon completion of the Lock bit set, or if no SPM instruction is executed within
four clock cycles.
An LPM instruction within three cycles after BLBSET and SPMEN are set in the
SPMCSR Register, will read either the Lock bits or the Fuse bits (depending on Z0 in
Bit
Read/Write
Initial Value
BOOTRST
1
0
1. “1” means unprogrammed, “0” means programmed
SPMIE
R/W
7
0
Reset Vector = Application Reset (address 0x0000)
Reset Vector = Boot Loader Reset (see Table 118 on page 321)
Reset Address
RWWSB
R
6
0
(1)
R
5
–
0
RWWSRE
R/W
4
0
BLBSET
R/W
3
0
PGWRT
R/W
2
0
PGERS
R/W
1
0
SPMEN
R/W
4250C–CAN–03/04
0
0
SPMCSR