AT90CAN128-16AE ATMEL Corporation, AT90CAN128-16AE Datasheet - Page 93

• Manufacturer Part Number: AT90CAN128-16AE
• Description: 8-bit Avr Microcontroller With 128K Bytes of Isp Flash And CAN Controller.flash (Kbytes) 128 Vcc (V) 2.7-5.5 EEPROM (Kbytes) 4 SRAM (bytes) 4K CAN (mess. Obj.) 15
• Manufacturer: ATMEL Corporation

Timer/Counter0/1/3
Prescalers
Register Description
General Timer/Counter
Control Register – GTCCR
4250C–CAN–03/04
T3
T1
T0
Synchronization
Synchronization
Synchronization
Enabling and disabling of the clock input must be done when T3/T1/T0 has been stable
for at least one system clock cycle, otherwise it is a risk that a false Timer/Counter clock
pulse is generated.
Each half period of the external clock applied must be longer than one system clock
cycle to ensure correct sampling. The external clock must be guaranteed to have less
than half the system clock frequency (f
the edge detector uses sampling, the maximum frequency of an external clock it can
detect is half the sampling frequency (Nyquist sampling theorem). However, due to vari-
ation of the system clock frequency and duty cycle caused by Oscillator source (crystal,
resonator, and capacitors) tolerances, it is recommended that maximum frequency of an
external clock source is less than f
An external clock source can not be prescaled.
Figure 35. Prescaler for Timer/Counter3, Timer/Counter1 and Timer/Counter0
CS00
CS01
CS02
Note:
• Bit 7 – TSM: Timer/Counter Synchronization Mode
Writing the TSM bit to one activates the Timer/Counter Synchronization mode. In this
mode, the value that is written to the PSR2 and PSR310 bits is kept, hence keeping the
corresponding prescaler reset signals asserted. This ensures that the corresponding
Timer/Counters are halted and can be configured to the same value without the risk of
one of them advancing during configuration. When the TSM bit is written to zero, the
PSR2 and PSR310 bits are cleared by hardware, and the Timer/Counters start counting
simultaneously.
Bit
Read/Write
Initial Value
TIMER/COUNTER0 CLOCK SOURCE
1. The synchronization logic on the input pins (
0
PSR310
CK
TSM
R
7
0
clk
T0
R
6
–
0
CS10
CS11
CS12
R
5
–
0
clk_I/O
Clear
TIMER/COUNTER1 CLOCK SOURCE
ExtClk
0
/2.5.
R
4
–
0
< f
10-BIT T/C PRESCALER
clk
clk_I/O
T1
R
3
–
0
T0/T1/T3)
/2) given a 50/50% duty cycle. Since
R
2
–
0
CS30
CS31
CS32
is shown in Figure 34.
AT90CAN128
PSR2
R/W
1
0
TIMER/COUNTER3 CLOCK SOURCE
0
PSR310
R/W
0
0
clk
T3
(1)
GTCCR
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