AT90CAN128-16AE ATMEL Corporation, AT90CAN128-16AE Datasheet - Page 173

• Manufacturer Part Number: AT90CAN128-16AE
• Description: 8-bit Avr Microcontroller With 128K Bytes of Isp Flash And CAN Controller.flash (Kbytes) 128 Vcc (V) 2.7-5.5 EEPROM (Kbytes) 4 SRAM (bytes) 4K CAN (mess. Obj.) 15
• Manufacturer: ATMEL Corporation

Clock Generation
Internal Clock Generation –
Baud Rate Generator
4250C–CAN–03/04
recovery units are used for asynchronous data reception. In addition to the recovery
units, the Receiver includes a Parity Checker, Control logic, a Shift Register and a two
level receive buffer (UDRn). The Receiver supports the same frame formats as the
Transmitter, and can detect Frame Error, Data OverRun and Parity Errors.
The Clock Generation logic generates the base clock for the Transmitter and Receiver.
The USARTn supports four modes of clock operation: Normal asynchronous, Double
Speed asynchronous, Master synchronous and Slave synchronous mode. The UMSELn
bit in USARTn Control and Status Register C (UCSRnC) selects between asynchronous
and synchronous operation. Double Speed (asynchronous mode only) is controlled by
the U2Xn found in the UCSRnA Register. When using synchronous mode (UMSELn =
1), the Data Direction Register for the XCKn pin (DDR_XCKn) controls whether the
clock source is internal (Master mode) or external (Slave mode). The XCKn pin is only
active when using synchronous mode.
Figure 81 shows a block diagram of the clock generation logic.
Figure 81. USARTn Clock Generation Logic, Block Diagram
Signal description:
Internal clock generation is used for the asynchronous and the synchronous master
modes of operation. The description in this section refers to Figure 81.
The USARTn Baud Rate Register (UBRRn) and the down-counter connected to it func-
tion as a programmable prescaler or baud rate generator. The down-counter, running at
system clock (
down to zero or when the UBRRnL Register is written. A clock is generated each time
the counter reaches zero. This clock is the baud rate generator clock output (=
f
or 16 depending on mode. The baud rate generator output is used directly by the
Receiver’s clock and data recovery units. However, the recovery units use a state
DDR_XCKn
clk
XCKn
txn clk Transmitter clock (Internal Signal).
rxn clk Receiver base clock (Internal Signal).
xn cki Input from XCK pin (internal Signal). Used for synchronous slave operation.
xn cko Clock output to XCK pin (Internal Signal). Used for synchronous master
f
Pin
clk
io
/(UBRRn+1)). The Transmitter divides the baud rate generator clock output by 2, 8
io
xn cko
xn cki
operation.
System I/O Clock frequency.
f
clk
clk
Down-Counter
io
Prescaling
io
Register
UBRRn
), is loaded with the UBRRn value each time the counter has counted
Sync
UBRRn+1
f
clk
UCPOLn
Detector
Edge
io
/2
/4
/2
AT90CAN128
DDR_XCKn
U2Xn
0
1
0
1
0
1
1
0
UMSELn
txn clk
rxn clk
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