AT90CAN128-16AE ATMEL Corporation, AT90CAN128-16AE Datasheet - Page 158

• Manufacturer Part Number: AT90CAN128-16AE
• Description: 8-bit Avr Microcontroller With 128K Bytes of Isp Flash And CAN Controller.flash (Kbytes) 128 Vcc (V) 2.7-5.5 EEPROM (Kbytes) 4 SRAM (bytes) 4K CAN (mess. Obj.) 15
• Manufacturer: ATMEL Corporation

Timer/Counter2 Interrupt Flag
Register – TIFR2
158
AT90CAN128
• Bit 0 – TOIE2: Timer/Counter2 Overflow Interrupt Enable
When the TOIE2 bit is written to one and the I-bit in the Status Register is set (one), the
Timer/Counter2 Overflow interrupt is enabled. The corresponding interrupt is executed if
a n o verflo w in Timer/Coun ter2 occurs, i.e ., when the TO V2 b it is set in th e
Timer/Counter2 Interrupt Flag Register – TIFR2.
• Bit 7..2 – Reserved Bits
These bits are reserved for future use.
• Bit 1 – OCF2A: Output Compare Flag 2 A
The OCF2A bit is set (one) when a compare match occurs between the Timer/Counter2
and the data in OCR2A – Output Compare Register2. OCF2A is cleared by hardware
when executing the corresponding interrupt handling vector. Alternatively, OCF2A is
c lea re d b y wr itin g a lo g ic o n e to th e flag . Wh e n th e I-b it in S RE G , O C IE2
(Timer/Counter2 Compare match Interrupt Enable), and OCF2A are set (one), the
Timer/Counter2 Compare match Interrupt is executed.
• Bit 0 – TOV2: Timer/Counter2 Overflow Flag
The TOV2 bit is set (one) when an overflow occurs in Timer/Counter2. TOV2 is cleared
by hardware when executing the corresponding interrupt handling vector. Alternatively,
TOV2 is cleared by writing a logic one to the flag. When the SREG I-bit, TOIE2A
( Tim er /Co u nte r2 O v er flo w In ter ru p t En ab le ), a n d TOV 2 ar e se t (o n e) , th e
Timer/Counter2 Overflow interrupt is executed. In PWM mode, this bit is set when
Timer/Counter2 changes counting direction at 0x00.
Bit
Read/Write
Initial Value
R
7
–
0
R
6
–
0
R
5
–
0
R
4
–
0
R
3
–
0
R
2
–
0
OCF2A
R/W
1
0
TOV2
R/W
0
0
4250C–CAN–03/04
TIFR2