AT90CAN128-16AE ATMEL Corporation, AT90CAN128-16AE Datasheet - Page 226

• Manufacturer Part Number: AT90CAN128-16AE
• Description: 8-bit Avr Microcontroller With 128K Bytes of Isp Flash And CAN Controller.flash (Kbytes) 128 Vcc (V) 2.7-5.5 EEPROM (Kbytes) 4 SRAM (bytes) 4K CAN (mess. Obj.) 15
• Manufacturer: ATMEL Corporation

Figure 104. Formats and States in the Slave Transmitter Mode
Miscellaneous States
Table 94. Miscellaneous States
Combining Several TWI
Modes
226
Status Code
(TWSR)
Prescaler Bits
are 0
0xF8
0x00
Reception of the
own slave address
and one or
more data bytes
Arbitration lost as master
and addressed as slave
Last data byte transmitted.
Switched to not addressed
slave (TWEA = '0')
AT90CAN128
Status of the Two-wire Serial
Bus and Two-wire Serial Inter-
face Hardware
No relevant state information
available; TWINT = “0”
Bus error due to an illegal
START or STOP condition
From master to slave
From slave to master
S
SLA
There are two status codes that do not correspond to a defined TWI state, see Table 94.
Status 0xF8 indicates that no relevant information is available because the TWINT flag
is not set. This occurs between other states, and when the TWI is not involved in a serial
transfer.
Status 0x00 indicates that a bus error has occurred during a Two-wire Serial Bus trans-
fer. A bus error occurs when a START or STOP condition occurs at an illegal position in
the format frame. Examples of such illegal positions are during the serial transfer of an
address byte, a data byte, or an acknowledge bit. When a bus error occurs, TWINT is
set. To recover from a bus error, the TWSTO flag must set and TWINT must be cleared
by writing a logic one to it. This causes the TWI to enter the not addressed slave mode
and to clear the TWSTO flag (no other bits in TWCR are affected). The SDA and SCL
lines are released, and no STOP condition is transmitted.
In some cases, several TWI modes must be combined in order to complete the desired
action. Consider for example reading data from a serial EEPROM. Typically, such a
transfer involves the following steps:
Application Software Response
To/from TWDR
No TWDR action
No TWDR action
R
DATA
$A8
$B0
A
A
n
To TWCR
STA
No TWCR action
0
A
STO
1
DATA
Any number of data bytes
and their associated acknowledge bits
This number (contained in TWSR) corresponds
to a defined state of the Two-wire Serial Bus. The
prescaler bits are zero or masked to zero
TWINT
1
TWEA
X
$B8
A
Wait or proceed current transfer
Only the internal hardware is affected, no STOP condi-
tion is sent on the bus. In all cases, the bus is released
and TWSTO is cleared.
DATA
Next Action Taken by TWI Hardware
$C0
$C8
A
A
P or S
All 1's
4250C–CAN–03/04
P or S