AT90CAN128-16AE ATMEL Corporation, AT90CAN128-16AE Datasheet - Page 294

• Manufacturer Part Number: AT90CAN128-16AE
• Description: 8-bit Avr Microcontroller With 128K Bytes of Isp Flash And CAN Controller.flash (Kbytes) 128 Vcc (V) 2.7-5.5 EEPROM (Kbytes) 4 SRAM (bytes) 4K CAN (mess. Obj.) 15
• Manufacturer: ATMEL Corporation

Boundary-scan and the Two-
wire Interface
294
AT90CAN128
Figure 143. General Port Pin Schematic Diagram
The two Two-wire Interface pins SCL and SDA have one additional control signal in the
scan-chain; Two-wire Interface Enable – TWIEN. As shown in Figure 144, the TWIEN
signal enables a tri-state buffer with slew-rate control in parallel with the ordinary digital
port pins. A general scan cell as shown in Figure 148 is attached to the TWIEN signal.
Notes:
See Boundary-scan
Description for Details!
1. A separate scan chain for the 50 ns spike filter on the input is not provided. The ordi-
2. Make sure the OC and TWIEN signals are not asserted simultaneously, as this will
Pxn
nary scan support for digital port pins suffice for connectivity tests. The only reason
for having TWIEN in the scan path, is to be able to disconnect the slew-rate control
buffer when doing boundary-scan.
lead to drive contention.
PUD:
PUExn:
OCxn:
ODxn:
IDxn:
SLEEP:
IDxn
PULLUP DISABLE
PULLUP ENABLE for pin Pxn
OUTPUT CONTROL for pin Pxn
OUTPUT DATA to pin Pxn
INPUT DATA from pin Pxn
SLEEP CONTROL
PUExn
SLEEP
OCxn
ODxn
SYNCHRONIZER
WDx:
RDx:
WPx:
RRx:
RPx:
CLK
D
L
Q
Q
I/O
:
D
WRITE DDRx
READ DDRx
WRITE PORTx
READ PORTx REGISTER
READ PORTx PIN
I/O CLOCK
PINxn
Q
Q
RESET
RESET
Q
Q
Q
Q
PORTxn
DDxn
CLR
CLR
D
D
4250C–CAN–03/04
CLK
PUD
WDx
RDx
WPx
RPx
RRx
I/O