AT90CAN128-16AE ATMEL Corporation, AT90CAN128-16AE Datasheet - Page 205

• Manufacturer Part Number: AT90CAN128-16AE
• Description: 8-bit Avr Microcontroller With 128K Bytes of Isp Flash And CAN Controller.flash (Kbytes) 128 Vcc (V) 2.7-5.5 EEPROM (Kbytes) 4 SRAM (bytes) 4K CAN (mess. Obj.) 15
• Manufacturer: ATMEL Corporation

Overview of the TWI
Module
Scl and SDA Pins
Bit Rate Generator Unit
4250C–CAN–03/04
The TWI module is comprised of several submodules, as shown in Figure 95. All regis-
ters drawn in a thick line are accessible through the AVR data bus.
Figure 95. Overview of the TWI Module
These pins interface the AVR TWI with the rest of the MCU system. The output drivers
contain a slew-rate limiter in order to conform to the TWI specification. The input stages
contain a spike suppression unit removing spikes shorter than 50 ns. Note that the inter-
nal pullups in the AVR pads can be enabled by setting the PORT bits corresponding to
the SCL and SDA pins, as explained in the I/O Port section. The internal pull-ups can in
some systems eliminate the need for external ones.
This unit controls the period of SCL when operating in a Master mode. The SCL period
is controlled by settings in the TWI Bit Rate Register (TWBR) and the Prescaler bits in
the TWI Status Register (TWSR). Slave operation does not depend on Bit Rate or Pres-
caler settings, but the CPU clock frequency in the slave must be at least 16 times higher
than the SCL frequency. Note that slaves may prolong the SCL low period, thereby
reducing the average TWI bus clock period. The SCL frequency is generated according
to the following equation:
•
•
Note:
TWBR = Value of the TWI Bit Rate Register
TWPS = Value of the prescaler bits in the TWI Status Register
Slew-rate
Address Match Unit
Control
Arbitration detection
START / STOP
Address Comparator
TWBR should be 10 or higher if the TWI operates in Master mode. If TWBR is lower than
10, the master may produce an incorrect output on SDA and SCL for the reminder of the
byte. The problem occurs when operating the TWI in Master mode, sending Start + SLA
+ R/W to a slave (a slave does not need to be connected to the bus for the condition to
happen).
Address Register
SCL
Control
(TWAR)
Spike
Filter
Bus Interface Unit
SCL frequency
Spike Suppression
Address/Data Shift
Register (TWDR)
Slew-rate
Control
SDA
=
Status Register
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
16
Ack
Spike
Filter
(TWSR)
+
2(TWBR) 4
State Machine and
CLKio
Control Unit
Status control
T W P S
Control Register
Bit Rate Generator
AT90CAN128
(TWCR)
Bit Rate Register
Prescaler
(TWBR)
TWI
Unit
205