AT90CAN128-16AE ATMEL Corporation, AT90CAN128-16AE Datasheet - Page 315

• Manufacturer Part Number: AT90CAN128-16AE
• Description: 8-bit Avr Microcontroller With 128K Bytes of Isp Flash And CAN Controller.flash (Kbytes) 128 Vcc (V) 2.7-5.5 EEPROM (Kbytes) 4 SRAM (bytes) 4K CAN (mess. Obj.) 15
• Manufacturer: ATMEL Corporation

Addressing the Flash
During Self-
Programming
4250C–CAN–03/04
the Z-pointer) into the destination register. See “Reading the Fuse and Lock Bits from
Software” on page 318 for details.
• Bit 2 – PGWRT: Page Write
If this bit is written to one at the same time as SPMEN, the next SPM instruction within
four clock cycles executes Page Write, with the data stored in the temporary buffer. The
page address is taken from the high part of the Z-pointer and the low part of RAMPZ.
The data in R1 and R0 are ignored. The PGWRT bit will auto-clear upon completion of a
Page Write, or if no SPM instruction is executed within four clock cycles. The CPU is
halted during the entire Page Write operation if the NRWW section is addressed.
• Bit 1 – PGERS: Page Erase
If this bit is written to one at the same time as SPMEN, the next SPM instruction within
four clock cycles executes Page Erase. The page address is taken from the high part of
the Z-pointer and the low part of RAMPZ. The data in R1 and R0 are ignored. The
PGERS bit will auto-clear upon completion of a Page Erase, or if no SPM instruction is
executed within four clock cycles. The CPU is halted during the entire Page Write oper-
ation if the NRWW section is addressed.
• Bit 0 – SPMEN: Store Program Memory Enable
This bit enables the SPM instruction for the next four clock cycles. If written to one
together with either RWWSRE, BLBSET, PGWRT’ or PGERS, the following SPM
instruction will have a special meaning, see description above. If only SPMEN is written,
the following SPM instruction will store the value in R1:R0 in the temporary page buffer
addressed by the Z-pointer/RAMPZ. The LSB of the Z-pointer is ignored. The SPMEN
bit will auto-clear upon completion of an SPM instruction, or if no SPM instruction is exe-
cuted within four clock cycles. During Page Erase and Page Write, the SPMEN bit
remains high until the operation is completed.
Writing any other combination than “10001”, “01001”, “00101”, “00011” or “00001” in the
lower five bits will have no effect.
The Z-pointer together with RAMPZ are used to address the SPM commands. For
details on how to use th RAMPZ, see “RAM Page Z Select Register – RAMPZ” on page
12.
Since the Flash is organized in pages (see Table 130 on page 328), the program
counter can be treated as having two different sections. One section, consisting of the
least significant bits, is addressing the words within a page, while the most significant
bits are addressing the pages. This is shown in Figure 152. Note that the page erase
and page write operations are addressed independently. Therefore it is of major impor-
tance that the Boot Loader software addresses the same page in both the page erase
and page write operation. Once a programming operation is initiated, the address is
latched and the Z-pointer/RAMPZ can be used for other operations.
The only SPM operation that does not use the Z-pointer/RAMPZ is setting the Boot
Loader Lock bits. The content of the Z-pointer/RAMPZ is ignored and will have no effect
on the operation. The (E)LPM instruction does also use the Z-pointer/RAMPZ to store
Bit
ZH (R31)
ZL (R30)
Z15
Z7
15
7
Z14
14
Z6
6
Z13
Z5
13
5
Z12
Z4
12
4
Z11
11
Z3
3
Z10
Z2
10
2
AT90CAN128
Z9
Z1
9
1
Z8
Z0
8
0
315