AT90CAN128-16AE ATMEL Corporation, AT90CAN128-16AE Datasheet - Page 184

• Manufacturer Part Number: AT90CAN128-16AE
• Description: 8-bit Avr Microcontroller With 128K Bytes of Isp Flash And CAN Controller.flash (Kbytes) 128 Vcc (V) 2.7-5.5 EEPROM (Kbytes) 4 SRAM (bytes) 4K CAN (mess. Obj.) 15
• Manufacturer: ATMEL Corporation

Disabling the Receiver
Flushing the Receive Buffer
Asynchronous Data
Reception
Asynchronous Clock
Recovery
184
AT90CAN128
In contrast to the Transmitter, disabling of the Receiver will be immediate. Data from
ongoing receptions will therefore be lost. When disabled (i.e., the RXENn is set to zero)
the Receiver will no longer override the normal function of the RxDn port pin. The
Receiver buffer FIFO will be flushed when the Receiver is disabled. Remaining data in
the buffer will be lost
The receiver buffer FIFO will be flushed when the Receiver is disabled, i.e., the buffer
will be emptied of its contents. Unread data will be lost. If the buffer has to be flushed
during normal operation, due to for instance an error condition, read the UDRn I/O loca-
tion until the RXCn flag is cleared.
The following code example shows how to flush the receive buffer.
Note:
The USARTn includes a clock recovery and a data recovery unit for handling asynchro-
nous data reception. The clock recovery logic is used for synchronizing the internally
generated baud rate clock to the incoming asynchronous serial frames at the RxDn pin.
The data recovery logic samples and low pass filters each incoming bit, thereby improv-
ing the noise immunity of the Receiver. The asynchronous reception operational range
depends on the accuracy of the internal baud rate clock, the rate of the incoming
frames, and the frame size in number of bits.
The clock recovery logic synchronizes internal clock to the incoming serial frames. Fig-
ure 84 illustrates the sampling process of the start bit of an incoming frame. The sample
rate is 16 times the baud rate for Normal mode, and eight times the baud rate for Double
Speed mode. The horizontal arrows illustrate the synchronization variation due to the
sampling process. Note the larger time variation when using the Double Speed mode
(U2Xn = 1) of operation. Samples denoted zero are samples done when the RxDn line
is idle (i.e., no communication activity).
Assembly Code Example
C Code Example
USART0_Flush:
void USART0_Flush (void )
{
}
lds
sbrs r16, RXC0
ret
lds
rjmp USART0_Flush
unsigned char dummy;
while (UCSR0A & (1<<RXC0) ) dummy = UDR0;
1. The example code assumes that the part specific header file is included.
r16, UCSR0A
r16, UDR0
(1)
(1)
4250C–CAN–03/04