AT90CAN128-16AE ATMEL Corporation, AT90CAN128-16AE Datasheet - Page 174
AT90CAN128-16AE
Manufacturer Part Number
AT90CAN128-16AE
Description
8-bit Avr Microcontroller With 128K Bytes of Isp Flash And CAN Controller.flash (Kbytes) 128 Vcc (V) 2.7-5.5 EEPROM (Kbytes) 4 SRAM (bytes) 4K CAN (mess. Obj.) 15
Manufacturer
ATMEL Corporation
Datasheet
1.AT90CAN128-16AE.pdf
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Double Speed Operation
(U2X)
External Clock
174
AT90CAN128
machine that uses 2, 8 or 16 states depending on mode set by the state of the UMSELn,
U2Xn and DDR_XCKn bits.
Table 76 contains equations for calculating the baud rate (in bits per second) and for
calculating the UBRRn value for each mode of operation using an internally generated
clock source.
Table 76. Equations for Calculating Baud Rate Register Setting
Note:
Some examples of UBRRn values for some system clock frequencies are found in Table
84 (see page 195).
The transfer rate can be doubled by setting the U2Xn bit in UCSRnA. Setting this bit
only has effect for the asynchronous operation. Set this bit to zero when using synchro-
nous operation.
Setting this bit will reduce the divisor of the baud rate divider from 16 to 8, effectively
doubling the transfer rate for asynchronous communication. Note however that the
Receiver will in this case only use half the number of samples (reduced from 16 to 8) for
data sampling and clock recovery, and therefore a more accurate baud rate setting and
system clock are required when this mode is used. For the Transmitter, there are no
downsides.
External clocking is used by the synchronous slave modes of operation. The description
in this section refers to Figure 81 for details.
External clock input from the XCKn pin is sampled by a synchronization register to mini-
mize the chance of meta-stability. The output from the synchronization register must
then pass through an edge detector before it can be used by the Transmitter and
Receiver. This process introduces a two CPU clock period delay and therefore the max-
imum external XCKn clock frequency is limited by the following equation:
Note that
mended to add some margin to avoid possible loss of data due to frequency variations.
Operating Mode
Asynchronous Normal
mode (U2Xn = 0)
Asynchronous Double
Speed mode (U2Xn = 1)
Synchronous Master
mode
BAUD
f
UBRRn Contents of the UBRRnH and UBRRnL Registers, (0-4095).
clk
io
1. The baud rate is defined to be the transfer rate in bit per second (bps)
f
clk
Baud rate (in bits per second, bps).
System I/O Clock frequency.
io
depends on the stability of the system clock source. It is therefore recom-
B A U D
B A U D
B A U D
Equation for Calculating
f
Baud Rate
X C K n
=
=
=
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
16
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
8
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
2
U B R R
U B R R
U B R R
f
- - - - - - - - - - - - - - - -
f
f
f
C L K i o
C L K i o
C L K i o
C L K i o
4
(1)
n
n
n
+
+
+
1
1
1
U B R R
Equation for Calculating
U B R R
U B R R
UBRRn Value
n
n
n
=
=
=
- - - - - - - - - - - - - - - - - - - - - - - -
16
- - - - - - - - - - - - - - - - - - - -
8
- - - - - - - - - - - - - - - - - - - -
2
f
f
f
B A U D
B A U D
C L K i o
C L K i o
C L K i o
4250C–CAN–03/04
B A U D
–
–
–
1
1
1
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