AT90CAN128-16AE ATMEL Corporation, AT90CAN128-16AE Datasheet - Page 172

• Manufacturer Part Number: AT90CAN128-16AE
• Description: 8-bit Avr Microcontroller With 128K Bytes of Isp Flash And CAN Controller.flash (Kbytes) 128 Vcc (V) 2.7-5.5 EEPROM (Kbytes) 4 SRAM (bytes) 4K CAN (mess. Obj.) 15
• Manufacturer: ATMEL Corporation

Overview
172
AT90CAN128
Many register and bit references in this section are written in general form.
A lower case “n” replaces the USART number, in this case 0 and 1. However, when
using the register or bit defines in a program, the precise form must be used, i.e., UDR0
for accessing USART0 I/O data value and so on.
A simplified block diagram of the USARTn Transmitter is shown in Figure 80. CPU
accessible I/O Registers and I/O pins are shown in bold.
Figure 80. USARTn Block Diagram
Note:
The dashed boxes in the block diagram separate the three main parts of the USARTn
(listed from the top): Clock Generator, Transmitter and Receiver. Control registers are
shared by all units. The Clock Generation logic consists of synchronization logic for
external clock input used by synchronous slave operation, and the baud rate generator.
The XCKn (Transfer Clock) pin is only used by synchronous transfer mode. The Trans-
mitter consists of a single write buffer, a serial Shift Register, Parity Generator and
Control logic for handling different serial frame formats. The write buffer allows a contin-
uous transfer of data without any delay between frames. The Receiver is the most
complex part of the USARTn module due to its clock and data recovery units. The
1. Refer to Figure 2 on page 4, Table 41 on page 79, and Table 36 on page 76 for
USARTn pin placement.
UCSRAn
TRANSMIT SHIFT REGISTER
RECEIVE SHIFT REGISTER
BAUD RATE GENERATOR
UDRn (Receive)
UDRn (Transmit)
UBRRn[H:L]
(1)
UCSRBn
GENERATOR
SYNC LOGIC
RECOVERY
RECOVERY
CHECKER
PARITY
CLOCK
PARITY
DATA
CLKio
Clock Generator
CONTROL
CONTROL
CONTROL
CONTROL
CONTROL
Transmitter
PIN
PIN
PIN
RX
TX
Receiver
UCSRCn
4250C–CAN–03/04
XCKn
RxDn
TxDn