AT90CAN128-16AE ATMEL Corporation, AT90CAN128-16AE Datasheet - Page 138

• Manufacturer Part Number: AT90CAN128-16AE
• Description: 8-bit Avr Microcontroller With 128K Bytes of Isp Flash And CAN Controller.flash (Kbytes) 128 Vcc (V) 2.7-5.5 EEPROM (Kbytes) 4 SRAM (bytes) 4K CAN (mess. Obj.) 15
• Manufacturer: ATMEL Corporation

Input Capture Register –
ICR1H and ICR1L
Input Capture Register –
ICR3H and ICR3L
Timer/Counter1 Interrupt
Mask Register – TIMSK1
Timer/Counter3 Interrupt
Mask Register – TIMSK3
138
AT90CAN128
The Input Capture is updated with the counter (TCNTn) value each time an event occurs
on the ICPn pin (or optionally on the Analog Comparator output for Timer/Counter1).
The Input Capture can be used for defining the counter TOP value.
The Input Capture Register is 16-bit in size. To ensure that both the high and low bytes
are read simultaneously when the CPU accesses these registers, the access is per-
formed using an 8-bit temporary high byte register (TEMP). This temporary register is
shared by all the other 16-bit registers. See “Accessing 16-bit Registers” on page 112
• Bit 7..6 – Reserved Bits
These bits are reserved for future use.
• Bit 5 – ICIEn: Input Capture Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts glo-
b ally ena ble d), th e Timer/Coun te rn Inpu t Ca pture interrup t is ena ble d. The
corresponding Interrupt Vector (See “Interrupts” on page 57 ) is executed when the ICFn
flag, located in TIFRn, is set.
• Bit 4 – Reserved Bit
This bit is reserved for future use.
• Bit 3 – OCIEnC: Output Compare C Match Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts glo-
bally enabled), the Timer/Countern Output Compare C Match interrupt is enabled. The
corresponding Interrupt Vector (See “Interrupts” on page 57 ) is executed when the
OCFnC flag, located in TIFRn, is set.
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
R/W
R/W
R
R
7
0
7
0
7
–
0
7
–
0
R/W
R/W
R
R
6
0
6
0
6
–
0
6
–
0
ICIE1
ICIE3
R/W
R/W
R/W
R/W
5
0
5
0
5
0
5
0
R/W
R/W
R
R
4
0
4
0
4
–
0
4
–
0
ICR1[15:8]
ICR3[15:8]
ICR1[7:0]
ICR3[7:0]
OCIE1C
OCIE3C
R/W
R/W
R/W
R/W
3
0
3
0
3
0
3
0
OCIE1B
OCIE3B
R/W
R/W
R/W
R/W
2
0
2
0
2
0
2
0
OCIE1A
OCIE3A
R/W
R/W
R/W
R/W
1
0
1
0
1
0
1
0
TOIE1
TOIE3
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
4250C–CAN–03/04
TIMSK1
TIMSK3
ICR1H
ICR1L
ICR3H
ICR3L