AT90CAN128-16AE ATMEL Corporation, AT90CAN128-16AE Datasheet - Page 175

• Manufacturer Part Number: AT90CAN128-16AE
• Description: 8-bit Avr Microcontroller With 128K Bytes of Isp Flash And CAN Controller.flash (Kbytes) 128 Vcc (V) 2.7-5.5 EEPROM (Kbytes) 4 SRAM (bytes) 4K CAN (mess. Obj.) 15
• Manufacturer: ATMEL Corporation

Synchronous Clock Operation When synchronous mode is used (UMSELn = 1), the XCKn pin will be used as either
Serial Frame
Frame Formats
4250C–CAN–03/04
clock input (Slave) or clock output (Master). The dependency between the clock edges
and data sampling or data change is the same. The basic principle is that data input (on
RxDn) is sampled at the opposite XCKn clock edge of the edge the data output (TxDn)
is changed.
Figure 82. Synchronous Mode XCKn Timing.
The UCPOLn bit UCRSnC selects which XCKn clock edge is used for data sampling
and which is used for data change. As Figure 82 shows, when UCPOLn is zero the data
will be changed at rising XCKn edge and sampled at falling XCKn edge. If UCPOLn is
set, the data will be changed at falling XCKn edge and sampled at rising XCKn edge.
A serial frame is defined to be one character of data bits with synchronization bits (start
and stop bits), and optionally a parity bit for error checking.
The USARTn accepts all 30 combinations of the following as valid frame formats:
•
•
•
•
A frame starts with the start bit followed by the least significant data bit. Then the next
data bits, up to a total of nine, are succeeding, ending with the most significant bit. If
enabled, the parity bit is inserted after the data bits, before the stop bits. When a com-
plete frame is transmitted, it can be directly followed by a new frame, or the
communication line can be set to an idle (high) state. Figure 83 illustrates the possible
combinations of the frame formats. Bits inside brackets are optional.
Figure 83. Frame Formats
St
(n)
UCPOLn = 1
UCPOLn = 0
1 start bit
5, 6, 7, 8, or 9 data bits
no, even or odd parity bit
1 or 2 stop bits
(IDLE)
Start bit, always low.
Data bits (0 to 8).
RxDn / TxDn
RxDn / TxDn
St
XCKn
XCKn
0
1
2
3
4
FRAME
[5]
[6]
[7]
[8]
[P]
Sample
Sample
AT90CAN128
Sp1 [Sp2]
(St / IDLE)
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