AT90CAN128-16AE ATMEL Corporation, AT90CAN128-16AE Datasheet - Page 13

• Manufacturer Part Number: AT90CAN128-16AE
• Description: 8-bit Avr Microcontroller With 128K Bytes of Isp Flash And CAN Controller.flash (Kbytes) 128 Vcc (V) 2.7-5.5 EEPROM (Kbytes) 4 SRAM (bytes) 4K CAN (mess. Obj.) 15
• Manufacturer: ATMEL Corporation

Instruction Execution
Timing
4250C–CAN–03/04
The Stack Pointer points to the data SRAM Stack area where the Subroutine and Inter-
rupt Stacks are located. This Stack space in the data SRAM must be defined by the
program before any subroutine calls are executed or interrupts are enabled. The Stack
Pointer must be set to point above 0x60. The Stack Pointer is decremented by one
when data is pushed onto the Stack with the PUSH instruction, and it is decremented by
two when the return address is pushed onto the Stack with subroutine call or interrupt.
The Stack Pointer is incremented by one when data is popped from the Stack with the
POP instruction, and it is incremented by two when data is popped from the Stack with
return from subroutine RET or return from interrupt RETI.
The AVR Stack Pointer is implemented as two 8-bit registers in the I/O space. The num-
ber of bits actually used is implementation dependent. Note that the data space in some
implementations of the AVR architecture is so small that only SPL is needed. In this
case, the SPH Register will not be present.
This section describes the general access timing concepts for instruction execution. The
AVR CPU is driven by the CPU clock clk
source for the chip. No internal clock division is used.
Figure 7 shows the parallel instruction fetches and instruction executions enabled by the
Harvard architecture and the fast-access Register File concept. This is the basic pipelin-
ing concept to obtain up to 1 MIPS per MHz with the corresponding unique results for
functions per cost, functions per clocks, and functions per power-unit.
Figure 7. The Parallel Instruction Fetches and Instruction Executions
Figure 8 shows the internal timing concept for the Register File. In a single clock cycle
an ALU operation using two register operands is executed, and the result is stored back
to the destination register.
Bit
Read/Write
Initial Value
2nd Instruction Execute
3rd Instruction Execute
1st Instruction Execute
2nd Instruction Fetch
3rd Instruction Fetch
4th Instruction Fetch
1st Instruction Fetch
SP15
SP7
R/W
R/W
clk
15
7
0
0
CPU
SP14
SP6
R/W
R/W
14
6
0
0
SP13
SP5
R/W
R/W
13
T1
5
0
0
SP12
SP4
R/W
R/W
12
CPU
4
0
0
, directly generated from the selected clock
SP11
SP3
R/W
R/W
T2
11
3
0
0
SP10
SP2
R/W
R/W
10
2
0
0
AT90CAN128
T3
R/W
R/W
SP9
SP1
9
1
0
0
SP8
SP0
R/W
R/W
8
0
0
0
T4
SPH
SPL
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