AT90CAN128-16AE ATMEL Corporation, AT90CAN128-16AE Datasheet - Page 91

• Manufacturer Part Number: AT90CAN128-16AE
• Description: 8-bit Avr Microcontroller With 128K Bytes of Isp Flash And CAN Controller.flash (Kbytes) 128 Vcc (V) 2.7-5.5 EEPROM (Kbytes) 4 SRAM (bytes) 4K CAN (mess. Obj.) 15
• Manufacturer: ATMEL Corporation

External Interrupt Mask
Register – EIMSK
External Interrupt Flag
Register – EIFR
4250C–CAN–03/04
• Bits 7..0 – INT7 – INT0: External Interrupt Request 7 - 0 Enable
When an INT7 – INT0 bit is written to one and the I-bit in the Status Register (SREG) is
set (one), the corresponding external pin interrupt is enabled. The Interrupt Sense Con-
trol bits in the External Interrupt Control Registers – EICRA and EICRB – defines
whether the external interrupt is activated on rising or falling edge or level sensed. Activ-
ity on any of these pins will trigger an interrupt request even if the pin is enabled as an
output. This provides a way of generating a software interrupt.
• Bits 7..0 – INTF7 - INTF0: External Interrupt Flags 7 - 0
When an edge or logic change on the INT7:0 pin triggers an interrupt request, INTF7:0
becomes set (one). If the I-bit in SREG and the corresponding interrupt enable bit,
INT7:0 in EIMSK, are set (one), the MCU will jump to the interrupt vector. The flag is
cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by
writing a logical one to it. These flags are always cleared when INT7:0 are configured as
level interrupt. Note that when entering sleep mode with the INT3:0 interrupts disabled,
the input buffers on these pins will be disabled. This may cause a logic change in inter-
nal signals which will set the INTF3:0 flags. See “Digital Input Enable and Sleep Modes”
on page 66 for more information.
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
INTF7
INT7
R/W
R/W
7
0
7
0
INTF6
INT6
R/W
R/W
6
0
6
0
INTF5
INT5
R/W
R/W
5
0
5
0
INTF4
INT4
R/W
R/W
4
0
4
0
INTF3
INT3
R/W
R/W
3
0
3
0
INTF2
INT2
R/W
R/W
2
0
2
0
AT90CAN128
INTF1
INT1
R/W
R/W
1
0
1
0
IINTF0
IINT0
R/W
R/W
0
0
0
0
EIMSK
EIFR
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