MT29C4G48MAZAPAKD-5 E IT Micron, MT29C4G48MAZAPAKD-5 E IT Datasheet
MT29C4G48MAZAPAKD-5 E IT
Related parts for MT29C4G48MAZAPAKD-5 E IT
MT29C4G48MAZAPAKD-5 E IT Summary of contents
Page 1
... Products and specifications discussed herein are subject to change by Micron without notice. 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP Figure 1: PoP Block Diagram NAND Flash Power LPDRAM Power 1 1 Micron Technology, Inc. reserves the right to change products or specifications without notice. Features NAND Flash NAND Flash Device Interface LPDRAM LPDRAM ...
Page 2
... NAND Flash Configuration Device Marking Due to the size of the package, the Micron-standard part number is not printed on the top of the device. Instead, an abbreviated device mark consisting of a 5-digit alphanumeric code is used. The abbreviated device marks are cross-referenced to the Micron part numbers at the FBGA Part Marking Decoder site: www.micron.com/decoder. ...
Page 3
... PROGRAM PAGE CACHE (80h-15h) ............................................................................................................ 75 PROGRAM PAGE TWO-PLANE (80h-11h) .................................................................................................... 78 PDF: 09005aef83ba4387 168ball_nand_lpddr_j42p_j4z2_j4z3_omap.pdf – Rev. H 3/11 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP 3 Micron Technology, Inc. reserves the right to change products or specifications without notice. Features © 2009 Micron Technology, Inc. All rights reserved. ...
Page 4
... DEEP POWER-DOWN ............................................................................................................................... 162 Truth Tables .................................................................................................................................................. 163 State Diagram ............................................................................................................................................... 168 PDF: 09005aef83ba4387 168ball_nand_lpddr_j42p_j4z2_j4z3_omap.pdf – Rev. H 3/11 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP 4 Micron Technology, Inc. reserves the right to change products or specifications without notice. Features © 2009 Micron Technology, Inc. All rights reserved. ...
Page 5
... Rev. B, Preliminary – 10/09 ........................................................................................................................ 218 Rev. A, Preliminary – 7/09 .......................................................................................................................... 218 PDF: 09005aef83ba4387 168ball_nand_lpddr_j42p_j4z2_j4z3_omap.pdf – Rev. H 3/11 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP 5 Micron Technology, Inc. reserves the right to change products or specifications without notice. Features © 2009 Micron Technology, Inc. All rights reserved. ...
Page 6
... Table 49: Target Output Drive Characteristics (One-Half Strength) ................................................................ 154 Table 50: Truth Table – Commands .............................................................................................................. 156 PDF: 09005aef83ba4387 168ball_nand_lpddr_j42p_j4z2_j4z3_omap.pdf – Rev. H 3/11 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP 6 Micron Technology, Inc. reserves the right to change products or specifications without notice. Features © 2009 Micron Technology, Inc. All rights reserved. ...
Page 7
... Table 54: Truth Table – CKE ......................................................................................................................... 167 Table 55: Burst Definition Table ................................................................................................................... 173 PDF: 09005aef83ba4387 168ball_nand_lpddr_j42p_j4z2_j4z3_omap.pdf – Rev. H 3/11 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP 7 Micron Technology, Inc. reserves the right to change products or specifications without notice. Features © 2009 Micron Technology, Inc. All rights reserved. ...
Page 8
... Figure 50: ERASE BLOCK TWO-PLANE (60h–D1h) Operation ......................................................................... 81 PDF: 09005aef83ba4387 168ball_nand_lpddr_j42p_j4z2_j4z3_omap.pdf – Rev. H 3/11 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP ) ................................................................................................................ ................................................................................................................ .............................................................................................................. Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2009 Micron Technology, Inc. All rights reserved. Features ...
Page 9
... Figure 100: INTERNAL DATA MOVE (85h-10h) with Random Data Input with Internal ECC Enabled .............. 133 Figure 101: ERASE BLOCK Operation ............................................................................................................ 133 PDF: 09005aef83ba4387 168ball_nand_lpddr_j42p_j4z2_j4z3_omap.pdf – Rev. H 3/11 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP 9 Micron Technology, Inc. reserves the right to change products or specifications without notice. Features © 2009 Micron Technology, Inc. All rights reserved. ...
Page 10
... NAND Flash and LPDDR PoP (TI OMAP) MCP t t DQSQ, QH, and Data Valid Window (x16) ................................................. 189 t t DQSQ, QH, and Data Valid Window (x32) ................................................. 190 and DQSCK ....................................................................................... 191 10 Micron Technology, Inc. reserves the right to change products or specifications without notice. Features © 2009 Micron Technology, Inc. All rights reserved. ...
Page 11
... LPDRAM devices in a single MCP. These products target mobile applications with low- power, high-performance, and minimal package-footprint design requirements. The NAND Flash and Mobile LPDRAM devices are also members of the Micron discrete mem- ory products portfolio. The NAND Flash and Mobile LPDRAM devices are packaged with separate interfaces (no shared address, control, data, or power balls) ...
Page 12
... BA1 NAND LPDDR Supply Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2009 Micron Technology, Inc. All rights reserved DNU DNU A DNU DNU SSQ DDQ DQ26 DQ27 D DQ28 ...
Page 13
... Output Ready/busy: Open-drain, active-LOW output that indicates when an internal operation is in progress. V Supply V : NAND power supply Micron Technology, Inc. reserves the right to change products or specifications without notice. Ball Assignments and Descriptions Description © 2009 Micron Technology, Inc. All rights reserved all SS ...
Page 14
... V Supply V : LPDDR power supply Supply V : LPDDR I/O power supply. DDQ DDQ V Supply V : LPDDR I/O ground. SSQ SSQ 14 Micron Technology, Inc. reserves the right to change products or specifications without notice. Ball Assignments and Descriptions Description 1 © 2009 Micron Technology, Inc. All rights reserved. J ...
Page 15
... DNU Do not use: Must be grounded or left floating. – connect: Not internally connected. 1 – RFU Reserved for future use. 15 Micron Technology, Inc. reserves the right to change products or specifications without notice. Description Description © 2009 Micron Technology, Inc. All rights reserved. ...
Page 16
... DDQ DDQ – Symbol DDQ – 16 Micron Technology, Inc. reserves the right to change products or specifications without notice. Electrical Specifications Min Max –1.0 2.4 1 –0.5 2.4 or (supply voltage 0.3V), whichever is less –55 +150 . DDQ Min Typ Max 1.70 1.80 1.95 1.70 1.80 1.95 – ...
Page 17
... CK CK# CKE0 RAS# CAS# WE# Address, BA0, BA1 PDF: 09005aef83ba4387 168ball_nand_lpddr_j42p_j4z2_j4z3_omap.pdf – Rev. H 3/11 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP NAND Flash LPDDR 17 Micron Technology, Inc. reserves the right to change products or specifications without notice. Device Diagrams V CC I/O R/ DDQ DM DQ ...
Page 18
... Rev. H 3/11 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP CE0# CLE ALE NAND Flash RE# WE# WP# CK CK# LPDDR (Die 0 and 1) RAS# CAS# WE# 18 Micron Technology, Inc. reserves the right to change products or specifications without notice. Device Diagrams V CC I/O R/ DDQ DM DQ DQS TQ V ...
Page 19
... ±0 0.5 TYP 11 CTR 12 ±0.1 19 Micron Technology, Inc. reserves the right to change products or specifications without notice. Package Dimensions Ball A1 ID 0.9 MAX 0.23 MIN © 2009 Micron Technology, Inc. All rights reserved. ...
Page 20
... ±0 0.5 TYP 11 CTR 12 ±0.1 20 Micron Technology, Inc. reserves the right to change products or specifications without notice. Package Dimensions Ball A1 ID 1.0 MAX 0.23 MIN © 2009 Micron Technology, Inc. All rights reserved. ...
Page 21
... ±0 0.5 TYP 11 CTR 12 ±0.1 21 Micron Technology, Inc. reserves the right to change products or specifications without notice. Package Dimensions Ball A1 ID 0.75 MAX 0.23 MIN © 2009 Micron Technology, Inc. All rights reserved. ...
Page 22
... NAND Flash and LPDDR PoP (TI OMAP) MCP 4Gb, 8Gb: x8, x16 NAND Flash Memory t WC: 20ns (3.3V), 25ns (1.8V 2.7–3. 1.7–1.95V CC 22 Micron Technology, Inc. reserves the right to change products or specifications without notice © 2009 Micron Technology, Inc. All rights reserved. ...
Page 23
... See Internal ECC and Spare Area Mapping for ECC for more information. PDF: 09005aef83ba4387 168ball_nand_lpddr_j42p_j4z2_j4z3_omap.pdf – Rev. H 3/11 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP 23 Micron Technology, Inc. reserves the right to change products or specifications without notice. General Description t R_ECC and © 2009 Micron Technology, Inc. All rights reserved. ...
Page 24
... The LOCK pin is used on the 1.8V device. Note: PDF: 09005aef83ba4387 168ball_nand_lpddr_j42p_j4z2_j4z3_omap.pdf – Rev. H 3/11 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP Address register Status register Command register 24 Micron Technology, Inc. reserves the right to change products or specifications without notice. Architecture Column decode NAND Flash array ...
Page 25
... CA4 LOW LOW PA5 PA4 BA13 BA12 LOW LOW 25 Micron Technology, Inc. reserves the right to change products or specifications without notice. Device and Array Organization DQ7 DQ0 1 page = ( bytes) 1 block = (2K + 64) bytes x 64 pages = (128K + 4K) bytes 1 plane = (128K + 4K) bytes x 2048 blocks ...
Page 26
... BA6 PA5 PA4 BA14 BA13 BA12 LOW LOW LOW 26 Micron Technology, Inc. reserves the right to change products or specifications without notice. Device and Array Organization DQ15 DQ0 1 page = ( words) 1 block = (1K + 32) words x 64 pages = (64K + 2K) words 1 plane = (64K + 2K) words x 2048 blocks ...
Page 27
... I/04 CA5 CA4 LOW LOW PA5 PA4 BA13 BA12 LOW LOW 27 Micron Technology, Inc. reserves the right to change products or specifications without notice. Device and Array Organization 2112 bytes I/O7 2048 64 I/O0 2048 64 1 page = ( bytes) 1 block = (2K + 64) bytes x 64 pages = (128K + 4K) bytes 1 plane = (128K + 4K) bytes x 2048 blocks ...
Page 28
... LOW LOW BA6 PA5 PA4 BA14 BA13 BA12 LOW LOW LOW 28 Micron Technology, Inc. reserves the right to change products or specifications without notice. Device and Array Organization 1056 words I/O7 1024 32 I/O0 1024 32 1 page = ( words) 1 block = (1K + 32) words x 64 pages = (64K + 2K) words ...
Page 29
... NAND Flash and LPDDR PoP (TI OMAP) MCP Asynchronous Interface Bus Operation CLE ALE WE Micron Technology, Inc. reserves the right to change products or specifications without notice. RE# I/ © 2009 Micron Technology, Inc. All rights reserved. WP# 0V/V ...
Page 30
... NAND Flash and LPDDR PoP (TI OMAP) MCP Asynchronous Interface Bus Operation t t CLS CLH ALS ALH COMMAND 30 Micron Technology, Inc. reserves the right to change products or specifications without notice. Don’t Care © 2009 Micron Technology, Inc. All rights reserved. ...
Page 31
... Asynchronous Interface Bus Operation ALS t ALH Col Col Row add 1 add 2 add 1 31 Micron Technology, Inc. reserves the right to change products or specifications without notice. Row Row add 2 add 3 Don’t Care Undefined © 2009 Micron Technology, Inc. All rights reserved. ...
Page 32
... Asynchronous Interface Bus Operation M Micron Technology, Inc. reserves the right to change products or specifications without notice. t CLH Don’t Care © 2009 Micron Technology, Inc. All rights reserved. ...
Page 33
... RC of 30ns or greater, the host can latch the data on the t REA t REA REH D D OUT OUT CHZ t REA t COH t RHZ t RHZ t RHOH D OUT Don’t Care Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2009 Micron Technology, Inc. All rights reserved. ...
Page 34
... Asynchronous Interface Bus Operation REH t REA t REA t RLOH D D OUT OUT 34 Micron Technology, Inc. reserves the right to change products or specifications without notice. t CHZ t COH t RHZ t RHOH D OUT Don’t Care is stable before issu- © 2009 Micron Technology, Inc. All rights reserved. ...
Page 35
... V (MAX Σ the sum of the input currents of all devices tied to the R/B# pin R/B# Open drain output I OL Device 35 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2009 Micron Technology, Inc. All rights reserved. ...
Page 36
... TC t Rise calculated at 10% and 90% points Fall - Rise are calculated at 10% and 90% points. 36 Micron Technology, Inc. reserves the right to change products or specifications without notice 3. Rise 1.8V CC © 2009 Micron Technology, Inc. All rights reserved. ...
Page 37
... Asynchronous Interface Bus Operation ) CC 3.50 3.00 2.50 2.00 1.50 1.00 0.50 0.00 0 2000 400 0 6000 ) 3.50 3.00 2.50 2.00 1.50 1.00 0.50 0.00 0 2000 4000 37 Micron Technology, Inc. reserves the right to change products or specifications without notice. 8000 10,000 12,000 Rp (Ω (MAX 6000 8000 10,000 Rp (Ω © 2009 Micron Technology, Inc. All rights reserved. 12,000 (MAX) ...
Page 38
... NAND Flash and LPDDR PoP (TI OMAP) MCP Asynchronous Interface Bus Operation 1200 1000 800 600 400 200 0 0 2000 4000 38 Micron Technology, Inc. reserves the right to change products or specifications without notice. 6000 8000 10,000 12,000 (MAX) Rp (Ω 100pF ...
Page 39
... Device Initialization Micron NAND Flash devices are designed to prevent data corruption during power tran- sitions. V protection during power transitions.) When ramping V to initialize the device: 1. Ramp V 2. The host must wait for R/ valid and HIGH before issuing RESET (FFh) to any target. The R/B# signal becomes valid when 50µs has elapsed since the begin- ning the not monitoring R/B#, the host must wait at least 100µ ...
Page 40
... Yes 10h 5 Yes 15h – 3 D0h – 5 35h 5 Optional 10h 40 Micron Technology, Inc. reserves the right to change products or specifications without notice. Command Definitions Valid While Valid While Selected LUN Other LUNs Busy are Busy Notes Yes Yes ...
Page 41
... Address mand Address Cycles Cycle #2 Cycles 5 00h 5 5 00h 5 – 5 E0h 41 Micron Technology, Inc. reserves the right to change products or specifications without notice. Command Definitions Valid While Valid While Selected LUN Other LUNs 1 Cycle #2 is Busy are Busy – No Yes – No Yes – ...
Page 42
... Cycles Cycle #2 Cycles 5 11h-80h 5 5 11h-80h 5 5 11h-85h 5 3 D1h-60h 3 42 Micron Technology, Inc. reserves the right to change products or specifications without notice. Command Definitions Com- Valid While Valid While mand Selected Other LUNs Cycle #3 LUN is Busy are Busy 10h No Yes 15h No ...
Page 43
... Rev. H 3/11 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP t RST after the RESET command is written to the Command Micron Technology, Inc. reserves the right to change products or specifications without notice. Reset Operations t RST © 2009 Micron Technology, Inc. All rights reserved. ...
Page 44
... Command Address D OUT t WHR 90h 00h Byte 0 Command Address D OUT t WHR 90h 20h 4Fh 44 Micron Technology, Inc. reserves the right to change products or specifications without notice. Identification Operations OUT OUT OUT OUT Byte 1 Byte 2 Byte 3 Byte OUT OUT ...
Page 45
... Micron Technology, Inc. reserves the right to change products or specifications without notice. READ ID Parameter Tables I/03 I/02 I/01 I/00 Value 2Ch DCh CCh ACh 1 ...
Page 46
... I/06 I/05 I/04 I/ Micron Technology, Inc. reserves the right to change products or specifications without notice. READ ID Parameter Tables I/04 I/03 I/02 I/01 I/ ...
Page 47
... PDF: 09005aef83ba4387 168ball_nand_lpddr_j42p_j4z2_j4z3_omap.pdf – Rev. H 3/11 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP D OUT 00h Micron Technology, Inc. reserves the right to change products or specifications without notice. READ PARAMETER PAGE (ECh OUT OUT OUT OUT P1 … ...
Page 48
... Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2009 Micron Technology, Inc. All rights reserved. ...
Page 49
... MT29F4G16ABBDA3W 1Fh, 00h MT29F8G08ADBDA3W 1Fh, 00h MT29F8G16ADBDA3W 1Fh, 00h MT29F4G08ABADA3W 3Fh, 00h MT29F4G16ABADA3W 3Fh, 00h MT29F8G08ADADA3W 3Fh, 00h MT29F8G16ADADA3W 3Fh, 00h 49 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2009 Micron Technology, Inc. All rights reserved. ...
Page 50
... Set at test 50 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2009 Micron Technology, Inc. All rights reserved. ...
Page 51
... EDh R/B# PDF: 09005aef83ba4387 168ball_nand_lpddr_j42p_j4z2_j4z3_omap.pdf – Rev. H 3/11 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP D OUT 00h Micron Technology, Inc. reserves the right to change products or specifications without notice. READ UNIQUE ID (EDh OUT OUT OUT OUT U1 … U0 ...
Page 52
... Programmable output drive strength 81h Programmable RB# pull-down strength 82h–FFh Reserved 90h Array operation mode 52 Micron Technology, Inc. reserves the right to change products or specifications without notice. Feature Operations t FEAT). t FEAT). The GET FEATURES command © 2009 Micron Technology, Inc. All rights reserved. ...
Page 53
... I/O4 I/O3 Reserved (0) Reserved (0) Reserved (0) Reserved (0) 0 Reserved (0) 1 Reserved (0) Reserved (0) Reserved (0) Command Address ADL I/O[7:0] EFh FA P1 R/B# 53 Micron Technology, Inc. reserves the right to change products or specifications without notice. Feature Operations I/O2 I/O1 I/O0 Value 0 00h 1 01h 1 1 03h 00h 08h 00h 00h 00h ...
Page 54
... I/Ox R/B# PDF: 09005aef83ba4387 168ball_nand_lpddr_j42p_j4z2_j4z3_omap.pdf – Rev. H 3/11 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP Command Address EEh FEAT Micron Technology, Inc. reserves the right to change products or specifications without notice. Feature Operations OUT OUT OUT OUT ...
Page 55
... Rev. H 3/11 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP I/O7 I/O6 I/O5 I/O4 I/O3 Reserved (0) Reserved (0) Reserved (0) Reserved (0) Reserved (0) Reserved (0) Reserved (0) Reserved (0) Reserved (0) 55 Micron Technology, Inc. reserves the right to change products or specifications without notice. Feature Operations I/O2 I/O1 I/O0 Value Notes 00h 01h 0 ...
Page 56
... NAND Flash and LPDDR PoP (TI OMAP) MCP I/O7 I/O6 I/O5 I/O4 I/O3 Reserved (0) Reserved (0) Reserved (0) Reserved (0) Reserved (0) Reserved (0) Reserved (0) I/O7 I/O6 I/O5 I/O4 I/O3 Reserved (0) Reserved (0) Reserved (0) 56 Micron Technology, Inc. reserves the right to change products or specifications without notice. Feature Operations I/O2 I/O1 I/O0 Value Notes 0 0 00h 0 1 01h 1 0 02h 1 1 03h 00h 00h 00h ...
Page 57
... Rewrite 3 recommended – – – Reserved 4 – FAIL 57 Micron Technology, Inc. reserves the right to change products or specifications without notice. Status Operations Block Erase Description 1 = Not protected RDY 0 = Busy 1 = Ready ARDY Don't Care – Don't Care – Normal or uncorrectable 1 = Rewrite recommended – ...
Page 58
... PDF: 09005aef83ba4387 168ball_nand_lpddr_j42p_j4z2_j4z3_omap.pdf – Rev. H 3/11 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP Command D OUT t WHR 70h SR 58 Micron Technology, Inc. reserves the right to change products or specifications without notice. Status Operations © 2009 Micron Technology, Inc. All rights reserved. ...
Page 59
... Rev. H 3/11 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP Command Address Address Address t WHR 78h Micron Technology, Inc. reserves the right to change products or specifications without notice. Status Operations D OUT SR © 2009 Micron Technology, Inc. All rights reserved. ...
Page 60
... NAND Flash and LPDDR PoP (TI OMAP) MCP Command Address Address Command t RHW 05h Micron Technology, Inc. reserves the right to change products or specifications without notice. Column Address Operations D D OUT OUT t WHR E0h © 2009 Micron Technology, Inc. All rights reserved. ...
Page 61
... NAND Flash and LPDDR PoP (TI OMAP) MCP t WHR before requesting data output. The selected die (LUN) Address Address Address Address Micron Technology, Inc. reserves the right to change products or specifications without notice. Column Address Operations Address Command D OUT t WHR R3 E0h © ...
Page 62
... Rev. H 3/11 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP D Command Address Address 85h Micron Technology, Inc. reserves the right to change products or specifications without notice. Column Address Operations t ADL before inputting data. As defined for PAGE (CACHE) PROGRAM ...
Page 63
... PDF: 09005aef83ba4387 168ball_nand_lpddr_j42p_j4z2_j4z3_omap.pdf – Rev. H 3/11 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP Column Address Operations t 63 Micron Technology, Inc. reserves the right to change products or specifications without notice. ADL before inputting data. The selec- © 2009 Micron Technology, Inc. All rights reserved. ...
Page 64
... Rev. H 3/11 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP Command Address Address Address Address 85h Micron Technology, Inc. reserves the right to change products or specifications without notice. Column Address Operations As defined for PAGE (CACHE) PROGRAM Address ADL ...
Page 65
... Rev. H 3/11 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP t R and the selected die (LUN) is busy (RDY = 0, ARDY = 0). After t RCBSY, R/B# goes HIGH and RDY = 1 and 65 Micron Technology, Inc. reserves the right to change products or specifications without notice. Read Operations t RCBSY while t RCBSY, t RCBSY while the data register is © ...
Page 66
... R and the selected die (LUN) is busy t R (R/B# is HIGH and RDY = 1, ARDY = 1), issue either of t RCBSY, R/B# goes HIGH and RDY = 1 and ARDY = 66 Micron Technology, Inc. reserves the right to change products or specifications without notice. Read Operations t RCBSY while t RCBSY, t RCBSY while the data registers are ...
Page 67
... NAND Flash and LPDDR PoP (TI OMAP) MCP t R_ECC) to determine whether an uncorrectable read t R_ECC is the data transferred with internal ECC enabled.) 67 Micron Technology, Inc. reserves the right to change products or specifications without notice. Read Operations data is © 2009 Micron Technology, Inc. All rights reserved. ...
Page 68
... NAND Flash and LPDDR PoP (TI OMAP) MCP Address Address Address Command Address Address Address 30h 68 Micron Technology, Inc. reserves the right to change products or specifications without notice. Read Operations D D OUT OUT 30h n R_ECC 70h ...
Page 69
... OUT 31h RCBSY RCBSY. After RCBSY, R/B# goes HIGH and the die (LUN Micron Technology, Inc. reserves the right to change products or specifications without notice. Read Operations D D Command OUT OUT … Dn 31h RCBSY t RR Page M © ...
Page 70
... Page Address N 31h Command D OUT 31h RCBSY t RR Page N 70 Micron Technology, Inc. reserves the right to change products or specifications without notice. Read Operations OUT OUT OUT D0 … RCBSY t RR Page M © 2009 Micron Technology, Inc. All rights reserved. ...
Page 71
... RCBSY, R/B# goes HIGH and the die (LUN Command OUT OUT OUT … D 3Fh Micron Technology, Inc. reserves the right to change products or specifications without notice. Read Operations D D OUT OUT D0 … RCBSY RR Page N © 2009 Micron Technology, Inc. All rights reserved. ...
Page 72
... Rev. H 3/11 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP t R. During these transfers, R/B# goes LOW. When the trans- 72 Micron Technology, Inc. reserves the right to change products or specifications without notice. Read Operations © 2009 Micron Technology, Inc. All rights reserved. ...
Page 73
... Column address J Col Col Row Row Row 06h D OUT add 1 add 2 add 1 add 2 add 3 Plane 1 address 73 Micron Technology, Inc. reserves the right to change products or specifications without notice. Read Operations Row Row Row 30h add 1 add 2 add Plane 1 address E0h ...
Page 74
... NAND Flash and LPDDR PoP (TI OMAP) MCP t t CBSY and LPROG, when RDY = 0 and ARDY = 0, the only valid commands are 74 Micron Technology, Inc. reserves the right to change products or specifications without notice. Program Operations © 2009 Micron Technology, Inc. All rights reserved. ...
Page 75
... PROG_ECC, the internal ECC generates parity bits when error detection is com- Address Address Address ADL Micron Technology, Inc. reserves the right to change products or specifications without notice. Program Operations Command Command IN IN … Dn 10h 70h t PROG or t ...
Page 76
... CBSY, the host can monitor the target's R/B# signal or, t CBSY, the host wants to wait for the program cache operation to complete, with- 76 Micron Technology, Inc. reserves the right to change products or specifications without notice. Program Operations © 2009 Micron Technology, Inc. All rights reserved. ...
Page 77
... Address Address Address IN t ADL Address Address Address ADL Micron Technology, Inc. reserves the right to change products or specifications without notice. Program Operations Command … Dn 15h CBSY Command … ...
Page 78
... CBSY. After CBSY, the host should check the status of the FAILC bit for 78 Micron Technology, Inc. reserves the right to change products or specifications without notice. Program Operations t PROG. When the die (LUN) is ready © 2009 Micron Technology, Inc. All rights reserved. ...
Page 79
... Rev. H 3/11 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP D Address Address Address IN t ADL Micron Technology, Inc. reserves the right to change products or specifications without notice. Program Operations D D Command Command IN IN … Dn 11h 80h DBSY © 2009 Micron Technology, Inc. All rights reserved. ...
Page 80
... Rev. H 3/11 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP Command Address Address Address 60h Micron Technology, Inc. reserves the right to change products or specifications without notice. Erase Operations Command D0h BERS © 2009 Micron Technology, Inc. All rights reserved. ...
Page 81
... DBSY, the host can monitor the target's R/B# signal, or Command Address Address Address 60h Micron Technology, Inc. reserves the right to change products or specifications without notice. Erase Operations Command Command Address D1h 60h DBSY © 2009 Micron Technology, Inc. All rights reserved. ...
Page 82
... DATA MOVE (85h-10h) command. See Two-Plane Operations for details. PDF: 09005aef83ba4387 168ball_nand_lpddr_j42p_j4z2_j4z3_omap.pdf – Rev. H 3/11 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP Internal Data Move Operations 82 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2009 Micron Technology, Inc. All rights reserved. ...
Page 83
... Address Address Address Address Command Address Command D OUT t WHR C2 E0h Dk 83 Micron Technology, Inc. reserves the right to change products or specifications without notice. Internal Data Move Operations Command D D OUT OUT 35h n OUT OUT 35h D0 … ...
Page 84
... SR bit READ error Address Address Address Address Address Micron Technology, Inc. reserves the right to change products or specifications without notice. Internal Data Move Operations t PROG_ECC Address 85h 10h 70h Status (5 cycles) Destination address SR bit READ successful SR bit READ error ...
Page 85
... R1 R2 Address Address WHR Address Address Address ADL Micron Technology, Inc. reserves the right to change products or specifications without notice. Internal Data Move Operations WHR Command 10h PROG D D ...
Page 86
... PDF: 09005aef83ba4387 168ball_nand_lpddr_j42p_j4z2_j4z3_omap.pdf – Rev. H 3/11 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP 86 Micron Technology, Inc. reserves the right to change products or specifications without notice. Block Lock Feature © 2009 Micron Technology, Inc. All rights reserved. ...
Page 87
... NAND Flash and LPDDR PoP (TI OMAP) MCP FFCh Upper block boundary FF8h Lower block boundary FFCh Upper block boundary FF8h Lower block boundary 87 Micron Technology, Inc. reserves the right to change products or specifications without notice. Block Lock Feature Protected area Unprotected area Protected area Unprotected Area ...
Page 88
... BA11 LOW LOW LOW LOW Block Block Block 23h add 1 add 2 add 3 Unlock Lower boundary 88 Micron Technology, Inc. reserves the right to change products or specifications without notice. Block Lock Feature I/O2 I/O1 I/O0 LOW LOW Invert area bit BA10 BA9 BA8 LOW BA17 BA16 Block ...
Page 89
... Figure 61: LOCK Operation CLE CE# WE# I/Ox PDF: 09005aef83ba4387 168ball_nand_lpddr_j42p_j4z2_j4z3_omap.pdf – Rev. H 3/11 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP 2Ah LOCK command 89 Micron Technology, Inc. reserves the right to change products or specifications without notice. Block Lock Feature © 2009 Micron Technology, Inc. All rights reserved. ...
Page 90
... NAND Flash and LPDDR PoP (TI OMAP) MCP t LBSY. The PROGRAM or ERASE operation does not LOCK WP# CLE CE# WE# 2Ch I/Ox LOCK TIGHT command R/B# 90 Micron Technology, Inc. reserves the right to change products or specifications without notice. Block Lock Feature © 2009 Micron Technology, Inc. All rights reserved. ...
Page 91
... I/O[7: CLE CE# WE# ALE RE# 7Ah Add 1 Add 2 Add 3 I/Ox BLOCK LOCK Block address READ STATUS 91 Micron Technology, Inc. reserves the right to change products or specifications without notice. Block Lock Feature t LBSY 70h READ STATUS I/O2 (Lock#) I/O1 (LT WHR Status © ...
Page 92
... WP# LOW >100ns or LOCK Cmd UNLOCK Cmd with invert area bit = 1 UNLOCK Cmd with invert area bit = 0 92 Micron Technology, Inc. reserves the right to change products or specifications without notice. Block Lock Feature Power-up with LOCK LOW (default) BLOCK LOCK function disabled ...
Page 93
... OTP DATA READ (AFh-30h), refer to the MT29F4GxxAxC data sheet. PDF: 09005aef83ba4387 168ball_nand_lpddr_j42p_j4z2_j4z3_omap.pdf – Rev. H 3/11 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP One-Time Programmable (OTP) Operations 93 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2009 Micron Technology, Inc. All rights reserved. ...
Page 94
... Status Operations). Each OTP page can be programmed to 8 partial-page programming. PDF: 09005aef83ba4387 168ball_nand_lpddr_j42p_j4z2_j4z3_omap.pdf – Rev. H 3/11 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP One-Time Programmable (OTP) Operations 94 Micron Technology, Inc. reserves the right to change products or specifications without notice. t PROG). The READ © 2009 Micron Technology, Inc. All rights reserved. ...
Page 95
... IN page bytes serial input OTP address 1 x8 device 2112 bytes x16 device 1056 words 95 Micron Technology, Inc. reserves the right to change products or specifications without notice PROG 10h 70h Status PROGRAM READ STATUS command command OTP data written (following good status confirmation) Don’ ...
Page 96
... D Col Col 00h IN IN 85h n n+1 add1 add2 Serial input RANDOM DATA Column address INPUT command t OBSY. 96 Micron Technology, Inc. reserves the right to change products or specifications without notice PROG 10h 70h n n+1 Serial input PROGRAM READ STATUS command command Don‘t Care © ...
Page 97
... One-Time Programmable (OTP) Operations Col OTP 00h 00h D page 00h IN PROGRAM command OTP address 97 Micron Technology, Inc. reserves the right to change products or specifications without notice PROG 10h 70h READ STATUS command OTP data protected © 2009 Micron Technology, Inc. All rights reserved. Status 1 ...
Page 98
... R) while the data is moved from the OTP page to the data register. The Col OTP 00h 00h 1 page OTP address OUT OUT 30h Busy Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2009 Micron Technology, Inc. All rights reserved. D OUT m Don’t Care ...
Page 99
... 00h 00h 30h OUT Busy 99 Micron Technology, Inc. reserves the right to change products or specifications without notice. t CLR t WHR t REA D Col Col OUT 05h E0h add 1 add 2 Column address m © 2009 Micron Technology, Inc. All rights reserved. ...
Page 100
... PDF: 09005aef83ba4387 168ball_nand_lpddr_j42p_j4z2_j4z3_omap.pdf – Rev. H 3/11 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP 100 Micron Technology, Inc. reserves the right to change products or specifications without notice. Two-Plane Operations © 2009 Micron Technology, Inc. All rights reserved. ...
Page 101
... Column address J Col Col Row Row D 06h OUT add 1 add 2 add 1 add 2 Plane 1 address 101 Micron Technology, Inc. reserves the right to change products or specifications without notice. Two-Plane Operations Page address M Col Row Row Row 30h add 1 add 2 add 3 Plane 1 address Row E0h ...
Page 102
... Data output 05h (2 cycles) Plane 1 data t DBSY input 11h 80h Address (5 cycles) 2nd-plane address 102 Micron Technology, Inc. reserves the right to change products or specifications without notice. Two-Plane Operations Address 05h E0h Data output (2 cycles) Plane 0 data E0h Data output Plane 1 data ...
Page 103
... Different column address than previous 5 address cycles, for 1st plane only Unlimited number of repetitions t PROG input 10h 103 Micron Technology, Inc. reserves the right to change products or specifications without notice. Two-Plane Operations t DBSY 11h 80h Address (5 cycles) Data input 2nd-plane address © 2009 Micron Technology, Inc. All rights reserved. ...
Page 104
... DBSY 11h 80h Address/data input 2nd plane t DBSY 11h Address/data input 80h 2nd plane 104 Micron Technology, Inc. reserves the right to change products or specifications without notice. Two-Plane Operations t CBSY 15h 1 t CBSY 15h 2 t LPROG 10h © 2009 Micron Technology, Inc. All rights reserved. ...
Page 105
... NAND Flash and LPDDR PoP (TI OMAP) MCP t R 00h Address (5 cycles) 35h 2nd-plane source t PROG 10h 70h Status 105 Micron Technology, Inc. reserves the right to change products or specifications without notice. Two-Plane Operations t DBSY 85h Address (5 cycles) 11h 1st-plane destination © 2009 Micron Technology, Inc. All rights reserved. 1 ...
Page 106
... Optional t DBSY 85h Address (5 cycles) 2nd-plane destination 106 Micron Technology, Inc. reserves the right to change products or specifications without notice. Two-Plane Operations 06h Address (5 cycles) 2nd-plane source address Data output Data from 2nd-plane source from new column address ...
Page 107
... Address (5 cycles) 2nd-plane source 1st-plane destination 85h 10h Data Address (2 cycles) Data Optional Unlimited number of repetitions 107 Micron Technology, Inc. reserves the right to change products or specifications without notice. Two-Plane Operations 85h 11h Data Address (2 cycles) Data Optional Unlimited number of repetitions t PROG 70h Status © ...
Page 108
... NAND Flash and LPDDR PoP (TI OMAP) MCP t DBSY Address input (3 cycles) D1h 60h 2nd plane Optional Address (3 cycles) 108 Micron Technology, Inc. reserves the right to change products or specifications without notice. Two-Plane Operations t BERS D0h 70h Status or 78h Don‘t Care t AR ...
Page 109
... This is because the 80h command clears the cache register contents of all cache regis- ters on all planes. PDF: 09005aef83ba4387 168ball_nand_lpddr_j42p_j4z2_j4z3_omap.pdf – Rev. H 3/11 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP Interleaved Die (Multi-LUN) Operations 109 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2009 Micron Technology, Inc. All rights reserved. ...
Page 110
... NAND Flash and LPDDR PoP (TI OMAP) MCP Requirement 4016 4096 x8: byte 2048 x16: word 1024 x8: 00h x16: 0000h 4-bit ECC per 528 bytes 110 Micron Technology, Inc. reserves the right to change products or specifications without notice. Error Management © 2009 Micron Technology, Inc. All rights reserved. ...
Page 111
... NAND Flash and LPDDR PoP (TI OMAP) MCP Requirement 4-bit ECC per 516 bytes (user data bytes (parity data) 1-bit ECC per 528 bytes 111 Micron Technology, Inc. reserves the right to change products or specifications without notice. Error Management © 2009 Micron Technology, Inc. All rights reserved. ...
Page 112
... User metadata II Spare 2 User metadata I Spare 2 ECC for main/spare 2 User data User metadata II Spare 3 User metadata I Spare 3 ECC for main/spare 3 112 Micron Technology, Inc. reserves the right to change products or specifications without notice. Bad Block ECC User Data Information Parity (Metadata) 2 bytes ...
Page 113
... User metadata II Spare 2 User metadata I Spare 2 ECC for main/spare 2 User data User metadata II Spare 3 User metadata I Spare 3 ECC for main/spare 3 113 Micron Technology, Inc. reserves the right to change products or specifications without notice. Bad Block ECC User Data Information Parity (Metadata) 1 word ...
Page 114
... T STG – Symbol T A Industrial 1. 3. Symbol Device Min NVB MT29F4G 4016 MT29F8G 8032 114 Micron Technology, Inc. reserves the right to change products or specifications without notice. Electrical Specifications Min Max Unit –0.6 2.4 V –0.6 4.6 V –0.6 2.4 V –0.6 4.6 V –65 150 °C – ...
Page 115
... C = 20pF) for MT29F8G 1.8V 3.3V 1 TTL GATE and CL = 30pF (1.8V) 1 TTL GATE and CL = 50pF (3.3V) 1 TTL GATE and CL = 30pF (1.8V) 1 TTL GATE and CL = 50pF (3.3V) 115 Micron Technology, Inc. reserves the right to change products or specifications without notice. Electrical Specifications Max Unit Value Notes 0. ...
Page 116
... I (R/B (RB#) may need to be relaxed if R/B pull-down strength is not set to full. and V may need to be relaxed if I/O drive strength is not set to full 116 Micron Technology, Inc. reserves the right to change products or specifications without notice. Typ Max Unit – – – ...
Page 117
... WP# – V –0 –100µ +100µ 0.2V I (R/B and 117 Micron Technology, Inc. reserves the right to change products or specifications without notice. Typ Max Unit – – – – – – µA – ...
Page 118
... 100 t ADL begins in the address cycle on the final rising edge of WE#, and ends 118 Micron Technology, Inc. reserves the right to change products or specifications without notice. Conditions Max Unit Notes – – ns – ns – ns – ns – ...
Page 119
... Symbol CEA t CHZ t CLR t COH REA t REH t RHOH t RHW 119 Micron Technology, Inc. reserves the right to change products or specifications without notice. Conditions Min Max Unit – – – – – – – ...
Page 120
... NAND Flash and LPDDR PoP (TI OMAP) MCP Electrical Specifications – AC Characteristics and Operating Symbol t RHZ t RLOH RST WHR 120 Micron Technology, Inc. reserves the right to change products or specifications without notice. Conditions Min Max Unit – – – – – ...
Page 121
... LBSY t PROG t PROG_ECC R_ECC t OBSY_ECC t DBSY t R_ECC is under typical process corner, nominal voltage, and at room temperature. 121 Micron Technology, Inc. reserves the right to change products or specifications without notice. Typ Max Unit Notes – 4 cycles 0 600 µ µs – ...
Page 122
... CLH CEA t WHR 70h 122 Micron Technology, Inc. reserves the right to change products or specifications without notice. t CHZ t COH RHZ t RHOH t REA Status output Don’t Care © 2009 Micron Technology, Inc. All rights reserved. ...
Page 123
... Asynchronous Interface Timing Diagrams ALH t ALS Row add 1 Row add 2 Row add R_ECC 123 Micron Technology, Inc. reserves the right to change products or specifications without notice CEA t ALH WHR t REA Status output P255 © ...
Page 124
... NAND Flash and LPDDR PoP (TI OMAP) MCP Asynchronous Interface Timing Diagrams R_ECC Row Row Row 30h add 1 add 2 add 3 124 Micron Technology, Inc. reserves the right to change products or specifications without notice. t CLR OUT OUT N ...
Page 125
... NAND Flash and LPDDR PoP (TI OMAP) MCP Asynchronous Interface Timing Diagrams R_ECC 30h t CEA CE REA CHZ t RE# COH Out I/Ox 125 Micron Technology, Inc. reserves the right to change products or specifications without notice. Data output Don’t Care © 2009 Micron Technology, Inc. All rights reserved. ...
Page 126
... Asynchronous Interface Timing Diagrams t RHW Col Col D 05h OUT OUT add 1 add 2 N Column address M 126 Micron Technology, Inc. reserves the right to change products or specifications without notice. t CLR t WHR t REA D D E0h OUT OUT © 2009 Micron Technology, Inc. All rights reserved. ...
Page 127
... CEA REA t DH Dout Dout Dout 0 1 Page address t RCBSY Column address 0 127 Micron Technology, Inc. reserves the right to change products or specifications without notice. t CEA REA t RR Dout Dout 31h Dout 0 1 Page address t RCBSY M Column address 0 ...
Page 128
... REA Dout Dout 31h RCBSY Page address M Column address 0 128 Micron Technology, Inc. reserves the right to change products or specifications without notice. Col Col Row Row 00h add 1 add 2 add 1 add 2 Column address Page address 00h N 1 tRHW Dout ...
Page 129
... D Row Row Row IN IN add 1 add 2 add byte serial Input 129 Micron Technology, Inc. reserves the right to change products or specifications without notice. Byte 2 Byte 3 Byte WHR PROG or t PROG_ECC 10h 70h © 2009 Micron Technology, Inc. All rights reserved. ...
Page 130
... ADL Row D D Col 85h IN IN add 3 add 1 add CHANGE WRITE Column address Serial input COLUMN command 130 Micron Technology, Inc. reserves the right to change products or specifications without notice. Data input t ADL t PROG PROG_ECC D Col D IN 10h Serial input © ...
Page 131
... Serial input Col Din Col Row Row 15h 70h Status 80h M add 1 add 2 add 1 add 2 Last page 131 Micron Technology, Inc. reserves the right to change products or specifications without notice. t ADL LPROG Row Row Row Din Din 10h add 1 add 2 add 3 N ...
Page 132
... Row 85h add 3 (or 30h) add 1 add 1 add 2 Busy D 70h Status 00h OUT D is optional OUT 132 Micron Technology, Inc. reserves the right to change products or specifications without notice. t ADL PROG Row Row Data Data 10h add 2 add READ STATUS ...
Page 133
... OUT D is optional Destination address OUT t WB BERS t Row D0h add 3 Busy 133 Micron Technology, Inc. reserves the right to change products or specifications without notice. t PROG_ECC Address Address Data 85h Data 10h (5 cycles) (2 cycles) Column address 1, 2 (Unlimitted repetitions are possible) t WHR ...
Page 134
... DDQ Reduced Page-Size 64 Meg x 32 Option 128 Meg Meg banks 8K 16K A[13:0] 1K A[9:0] 134 Micron Technology, Inc. reserves the right to change products or specifications without notice. Reduced Page-Size Option 64 Meg Meg banks 8K 8K 32K A[14:0] 32K A[14:0] 1K A[9:0] 512K A[8:0] ...
Page 135
... Any specific requirement takes precedence over a general statement. PDF: 09005aef83ba4387 168ball_nand_lpddr_j42p_j4z2_j4z3_omap.pdf – Rev. H 3/11 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP 2Gb: x16, x32 Mobile LPDDR SDRAM 135 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2009 Micron Technology, Inc. All rights reserved. ...
Page 136
... Sense amplifiers I/O gating DM mask logic 32 Bank control logic Column decoder Column- address counter/ latch 1 136 Micron Technology, Inc. reserves the right to change products or specifications without notice. Functional Block Diagrams Data 16 16 Read MUX latch DRVRS 16 2 DQS generator COL 0 DQS Input ...
Page 137
... Sense amplifiers I/O gating DM mask logic 64 Bank control logic Column decoder Column- address counter/ latch 1 137 Micron Technology, Inc. reserves the right to change products or specifications without notice. Functional Block Diagrams Data 32 32 Read MUX latch DRVRS 32 2 DQS generator COL 0 DQS Input ...
Page 138
... IL(DC) V 0.8 × V IH(AC) V –0.3 IL(AC) = –0.1mA) V 0.9 × 0.1mA 138 Micron Technology, Inc. reserves the right to change products or specifications without notice. Electrical Specifications Min Max –1.0 2.4 –0.5 2 0.3V), DDQ whichever is less –55 150 must not exceed DDQ Max Unit 1 ...
Page 139
... CK and the input lev expected to equal and DH for each 100 mV/ns reduction in slew rate. If slew rate exceeds 139 Micron Technology, Inc. reserves the right to change products or specifications without notice. Electrical Specifications Max Unit μA 1 ˚C 85 ˚ ...
Page 140
... DCK DIO /V DD DDQ /2, V (peak-to-peak) = 0.2V. DM input is grouped with I/O pins, reflecting the DDQ OUT 140 Micron Technology, Inc. reserves the right to change products or specifications without notice. Electrical Specifications Min Max Unit 1.5 3.5 pF – 0.25 pF 1.5 3.5 pF – 0.5 pF 2.0 4.5 pF – ...
Page 141
... CK (MIN); I 130 DD4W t RFC = 138ns I 170 DD5 t t RFC = REFI I 12 DD5A I 10 DD8 141 Micron Technology, Inc. reserves the right to change products or specifications without notice. Parameters DD Max -54 -6 -75 Unit Notes 100 μA 900 900 900 7, 8 μA 900 ...
Page 142
... CK I 150 DD4W t RFC = 138ns I 170 DD5 t t RFC = REFI I 12 DD5A I 10 DD8 142 Micron Technology, Inc. reserves the right to change products or specifications without notice. Parameters DD Max -54 -6 -75 Unit Notes 100 μA 900 900 900 7, 8 μA 900 ...
Page 143
... CK (MIN); I 130 DD4W t RFC = 138ns I 170 DD5 t t RFC = REFI I 13 DD5A I 15 DD8 143 Micron Technology, Inc. reserves the right to change products or specifications without notice. Parameters DD Max -54 -6 -75 Unit Notes 100 μA 1500 1500 1500 7, 8 μA 1500 ...
Page 144
... CK I 150 DD4W t RFC = 138ns I 170 DD5 t t RFC = REFI I 13 DD5A I 15 DD8 144 Micron Technology, Inc. reserves the right to change products or specifications without notice. Parameters DD Max -54 -6 -75 Unit Notes 100 μA 1500 1500 1500 7, 8 μA 1500 ...
Page 145
... DQ, DQS, and driven to a valid high or low logic level. t RFC later. t RFC (MIN)) else CKE is LOW (for example, during standby). 85˚C are guaranteed for the entire temperature range. All other I DD6 145 Micron Technology, Inc. reserves the right to change products or specifications without notice. Parameters 1.70–1.95V DD DDQ Symbol ...
Page 146
... PDF: 09005aef83ba4387 168ball_nand_lpddr_j42p_j4z2_j4z3_omap.pdf – Rev. H 3/11 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP Electrical Specifications – Temperature ('C) 146 Micron Technology, Inc. reserves the right to change products or specifications without notice. Parameters © 2009 Micron Technology, Inc. All rights reserved. ...
Page 147
... Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2009 Micron Technology, Inc. All rights reserved. Unit Notes – 13, 14 13, 14 ...
Page 148
... Micron Technology, Inc. reserves the right to change products or specifications without notice. -6 -75 Max Min Max Unit DQSQ QH - DQSQ ns – t – CH – – 5.0 6.0 ns – ...
Page 149
... SS 50 I/O I/O 20pF Full drive strength Half drive strength 149 Micron Technology, Inc. reserves the right to change products or specifications without notice. -6 -75 Min Max Min Max Unit – – 18 22.5 t 0.9 1.1 0.9 1.1 t 0.5 1.1 0.5 1.1 t 0.4 ...
Page 150
... LZ transitions occur in the same access time windows as valid data transitions. t HZ) or begins driving ( t DQSCK (MAX DQSS. 150 Micron Technology, Inc. reserves the right to change products or specifications without notice CKE, CKE starts at the rising edge to V for rising input signals and V ...
Page 151
... NAND Flash and LPDDR PoP (TI OMAP) MCP Electrical Specifications – AC Operating Conditions t WR time when in auto precharge mode REF = 151 Micron Technology, Inc. reserves the right to change products or specifications without notice. t XSR period REF /2 and REF I = REF I/2 . © 2009 Micron Technology, Inc. All rights reserved. ...
Page 152
... Max 0.00 18.53 26.80 32.80 37.05 40.00 42.50 44.57 46.50 47.48 48.50 49.40 50.05 51.35 52.65 53.95 55.25 56.55 57.85 59.15 – 60.45 – 61.75 152 Micron Technology, Inc. reserves the right to change products or specifications without notice. Output Drive Characteristics Pull-Up Current (mA) Min Max 0.00 0.00 –2.80 –18.53 –5.60 –26.80 –8.40 –32.80 –11.20 –37.05 –14.00 –40.00 –16.80 –42.50 –19.60 –44.57 –22.40 –46.50 –23.80 –47.48 –23.80 – ...
Page 153
... Max 0.00 12.97 18.76 22.96 25.94 28.00 29.75 31.20 32.55 33.24 33.95 34.58 35.04 35.95 36.86 37.77 38.68 39.59 40.50 41.41 – 42.32 – 43.23 153 Micron Technology, Inc. reserves the right to change products or specifications without notice. Output Drive Characteristics Pull-Up Current (mA) Min Max 0.00 0.00 –1.96 –12.97 –3.92 –18.76 –5.88 –22.96 –7.84 –25.94 –9.80 –28.00 –11.76 –29.75 –13.72 –31.20 –15.68 –32.55 –16.66 –33.24 –16.66 – ...
Page 154
... Max 0.00 8.42 12.30 14.95 16.84 18.20 19.30 20.30 21.20 21.60 22.00 22.45 22.73 23.21 23.67 24.14 24.61 25.08 25.54 26.01 – 26.48 – 26.95 154 Micron Technology, Inc. reserves the right to change products or specifications without notice. Output Drive Characteristics Pull-Up Current (mA) Min Max 0.00 0.00 –1.27 –8.42 –2.55 –12.30 –3.82 –14.95 –5.09 –16.84 –6.36 –18.20 –7.64 –19.30 –8.91 –20.30 –10.16 –21.20 –10.80 –21.60 –10.80 – ...
Page 155
... It has been omitted to save power. PDF: 09005aef83ba4387 168ball_nand_lpddr_j42p_j4z2_j4z3_omap.pdf – Rev. H 3/11 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP 155 Micron Technology, Inc. reserves the right to change products or specifications without notice. Functional Description © 2009 Micron Technology, Inc. All rights reserved. ...
Page 156
... 156 Micron Technology, Inc. reserves the right to change products or specifications without notice. Commands WE# Address Notes Bank/row 2 H Bank/column 3 L Bank/column Code ...
Page 157
... CHARGE command is issued to that bank. A PRECHARGE command must be issued before opening a different row in the same bank. PDF: 09005aef83ba4387 168ball_nand_lpddr_j42p_j4z2_j4z3_omap.pdf – Rev. H 3/11 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP 157 Micron Technology, Inc. reserves the right to change products or specifications without notice. Commands DQ Notes Valid MRD is met. © ...
Page 158
... PDF: 09005aef83ba4387 168ball_nand_lpddr_j42p_j4z2_j4z3_omap.pdf – Rev. H 3/11 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP CK HIGH CS# Row Bank Don’t Care 158 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2009 Micron Technology, Inc. All rights reserved. Commands ...
Page 159
... NAND Flash and LPDDR PoP (TI OMAP) MCP CK CKE HIGH CS# Column EN AP DIS AP Bank Don’t Care 159 WTR are satisfied. Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2009 Micron Technology, Inc. All rights reserved. Commands ...
Page 160
... NAND Flash and LPDDR PoP (TI OMAP) MCP CK HIGH CS# Column EN AP DIS AP Bank Don’t Care t RP) after the PRECHARGE command is issued. Input A10 determines 160 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2009 Micron Technology, Inc. All rights reserved. Commands ...
Page 161
... Rev. H 3/11 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP CK HIGH CS# All banks Single bank Bank Don’t Care 161 t RFC later. Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2009 Micron Technology, Inc. All rights reserved. Commands ...
Page 162
... Care” with the exception of CKE, which must re- main LOW. Micron recommends that, prior to self refresh entry and immediately upon self refresh exit, the user perform a burst auto refresh cycle for the number of refresh rows. Alterna- tively distributed refresh pattern is used, this pattern should be immediately resumed upon self refresh exit ...
Page 163
... RP is met, the bank will be in the idle state. t RCD is met, the bank will be in the row active state. 163 Micron Technology, Inc. reserves the right to change products or specifications without notice. Truth Tables t is HIGH and after XSR has been met (if ...
Page 164
... MRD has been met. After MRD is met, the device will be in the all met, all banks will be in the idle state. 164 Micron Technology, Inc. reserves the right to change products or specifications without notice. Truth Tables met, the bank will t ...
Page 165
... WRITE (select column and start new WRITE burst PRECHARGE was HIGH, CKE 165 Micron Technology, Inc. reserves the right to change products or specifications without notice. Truth Tables t is HIGH and after XSR has been met ( has been met (if the previous state was power has been met ...
Page 166
... WRITE or WRITE with auto precharge PRECHARGE ACTIVE READ or READ with auto precharge WRITE or WRITE with auto precharge PRECHARGE ACTIVE 166 Micron Technology, Inc. reserves the right to change products or specifications without notice. Truth Tables t WR measured as if auto Minimum Delay (with Concurrent Auto Precharge) t ...
Page 167
... ACTION XSR period. 167 Micron Technology, Inc. reserves the right to change products or specifications without notice. Truth Tables ACTION n Maintain active power-down Maintain deep power-down Maintain precharge power-down Maintain self refresh Exit active power-down ...
Page 168
... DPDX = Exit deep power-down EMR = LOAD EXTENDED MODE REGISTER LMR = LOAD MODE REGISTER PRE = PRECHARGE PREALL = PRECHARGE all banks READ = READ w/o auto precharge 168 Micron Technology, Inc. reserves the right to change products or specifications without notice. State Diagram READ READ SRR AREF Auto ...
Page 169
... Standard initialization requires that CKE be asserted DD t RFC time. Issue a second AUTO REFRESH command followed by NOP t RFC time. Two AUTO REFRESH commands 169 Micron Technology, Inc. reserves the right to change products or specifications without notice. Initialization DDQ t IS prior to T0 (see Figure 112 t RP time. ...
Page 170
... High High RFC 170 Micron Technology, Inc. reserves the right to change products or specifications without notice. Initialization Tc0 Td0 Te0 ( ( ( ( ( ( ( ) ) ) ) ) ) ) ( ( ( ( ( ( ( ) ) ) ) ) ) ) ( ( ( ...
Page 171
... PRE ( ( ( ( ) ) ) ) 171 Micron Technology, Inc. reserves the right to change products or specifications without notice. Initialization Tc0 Td0 Te0 ( ( ( ( ( ( ( ( ) ) ) ) ) ) ) ) ( ( ( ( ( ( ( ( ) ) ) ) ) ) ) ...
Page 172
... Reserved Reserved Reserved 172 Micron Technology, Inc. reserves the right to change products or specifications without notice. Standard Mode Register t MRD before initiating the subse Address bus Standard mode register (Mx) ...
Page 173
... Type = Sequential A0 0 0 0-1-2 1-2-3 2-3-0 3-0-1 0-1-2-3-4-5-6 1-2-3-4-5-6-7 2-3-4-5-6-7-0 3-4-5-6-7-0-1 4-5-6-7-0-1-2 5-6-7-0-1-2-3 6-7-0-1-2-3-4 7-0-1-2-3-4-5-6 A0 173 Micron Technology, Inc. reserves the right to change products or specifications without notice. Standard Mode Register Type = Interleaved 0-1 1-0 0-1-2-3 1-0-3-2 2-3-0-1 3-2-1-0 0-1-2-3-4-5-6-7 1-0-3-2-5-4-7-6 2-3-0-1-6-7-4-5 3-2-1-0-7-6-5-4 4-5-6-7-0-1-2-3 5-4-7-6-1-0-3-2 6-7-4-5-2-3-0-1 7-6-5-4-3-2-1-0 © 2009 Micron Technology, Inc. All rights reserved. ...
Page 174
... A-B-C-D-E-F-0-1-2-3-4-5-6-7-8 B-C-D-E-F-0-1-2-3-4-5-6-7-8-9 C-D-E-F-0-1-2-3-4-5-6-7-8-9-A D-E-F-0-1-2-3-4-5-6-7-8-9-A-B E-F-0-1-2-3-4-5-6-7-8-9-A-B-C F-0-1-2-3-4-5-6-7-8-9-A-B-C-D-E t AC). For the READ command is regis- 174 Micron Technology, Inc. reserves the right to change products or specifications without notice. Standard Mode Register Type = Interleaved 0-1-2-3-4-5-6-7-8-9-A-B-C-D-E-F 1-0-3-2-5-4-7-6-9-8-B-A-D-C-F-E 2-3-0-1-6-7-4-5-A-B-8-9-E-F-C-D 3-2-1-0-7-6-5-4-B-A-9-8-F-E-D-C 4-5-6-7-0-1-2-3-C-D-E-F-8-9-A-B 5-4-7-6-1-0-3-2-D-C-F-E-9-8-B-A 6-7-4-5-2-3-0-1-E-F-C-D-A-B-8-9 7-6-5-4-3-2-1-0-F-E-D-C-B-A-9-8 8-9-A-B-C-D-E-F-0-1-2-3-4-5-6-7 9-8-B-A-D-C-F-E-1-0-3-2-5-4-7-6 A-B-8-9-E-F-C-D-2-3-0-1-6-7-4-5 B-A-9-8-F-E-D-C-3-2-1-0-7-6-5-4 C-D-E-F-8-9-A-B-4-5-6-7-0-1-2-3 D-C-F-E-9-8-B-A-5-4-7-6-1-0-3-2 E-F-C-D-A-B-8-9-6-7-4-5-2-3-0-1 F-E-D-C-B-A-9-8-7-6-5-4-3-2-1-0 t AC). © 2009 Micron Technology, Inc. All rights reserved. ...
Page 175
... T0 T1 T1n CK READ NOP READ NOP Transitioning Data 175 Micron Technology, Inc. reserves the right to change products or specifications without notice. Standard Mode Register T2 T2n T3 T3n NOP NOP OUT OUT OUT OUT ...
Page 176
... E7–E0 Normal AR operation Valid All other states reserved – 176 Micron Technology, Inc. reserves the right to change products or specifications without notice. Extended Mode Register Address bus Extended mode 1 TCSR PASR register (Ex Partial-Array Self Refresh Coverage ...
Page 177
... PDF: 09005aef83ba4387 168ball_nand_lpddr_j42p_j4z2_j4z3_omap.pdf – Rev. H 3/11 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP 177 Micron Technology, Inc. reserves the right to change products or specifications without notice. Extended Mode Register © 2009 Micron Technology, Inc. All rights reserved. ...
Page 178
... SRR 2 NOP LMR READ 0 BA0 = 1 BA1 = 0 SRR), and between the READ and the next VALID command ( 178 Micron Technology, Inc. reserves the right to change products or specifications without notice. Status Read Register t t SRC after the SRR READ com SRC NOP ...
Page 179
... IBIS (pull pull-down characteristics), or process occurs 179 Micron Technology, Inc. reserves the right to change products or specifications without notice. Status Read Register I/O bus (CLK L->H edge) DQ4 DQ3 DQ2 DQ1 DQ0 ...
Page 180
... ACTIVE commands to different banks is defined t by RRD. PDF: 09005aef83ba4387 168ball_nand_lpddr_j42p_j4z2_j4z3_omap.pdf – Rev. H 3/11 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP t RCD specification. 180 Micron Technology, Inc. reserves the right to change products or specifications without notice. Bank/Row Activation t RC. © 2009 Micron Technology, Inc. All rights reserved. ...
Page 181
... NAND Flash and LPDDR PoP (TI OMAP) MCP t DQSQ (valid data-out skew), t DQSCK (DQS transition skew to CK) and 181 Micron Technology, Inc. reserves the right to change products or specifications without notice. READ Operation t QH (data-out © 2009 Micron Technology, Inc. All rights reserved. ...
Page 182
... T2 T2n T3 NOP NOP OUT n = data-out from column n. OUT t t AC, DQSCK, and 182 Micron Technology, Inc. reserves the right to change products or specifications without notice. READ Operation met. Part of the row precharge T3n T4 T5 NOP NOP OUT T3n T4 T5 ...
Page 183
... READ NOP Bank, Col OUT data-out from column n (or column b). OUT t t AC, DQSCK, and 183 Micron Technology, Inc. reserves the right to change products or specifications without notice. READ Operation T3n T4 T4n T5 T5n NOP NOP OUT OUT ...
Page 184
... NOP READ Bank, Col OUT data-out from column n (or column b). OUT t t AC, DQSCK, and 184 Micron Technology, Inc. reserves the right to change products or specifications without notice. READ Operation T3n T4 T4n T5 T5n NOP NOP OUT OUT ...
Page 185
... Bank, Col x Col OUT data-out from column n (or column x, column b, column g). OUT t t AC, DQSCK, and 185 Micron Technology, Inc. reserves the right to change products or specifications without notice. READ Operation T3 T3n T4 T4n T5 NOP NOP Col ...
Page 186
... T1 T2 T2n 2 BST NOP OUT data-out from column n. OUT t t AC, DQSCK, and 186 Micron Technology, Inc. reserves the right to change products or specifications without notice. READ Operation NOP NOP NOP T3 T3n T4 T5 NOP NOP NOP D OUT Don’t Care ...
Page 187
... T2n 2 BST NOP NOP OUT data-out from column n. OUT b = data-in from column AC, DQSCK, and 187 Micron Technology, Inc. reserves the right to change products or specifications without notice. READ Operation T3 T3n T4 T4n T5 1 NOP NOP t DQSS (NOM ...
Page 188
... T2 T2n 2 NOP PRE Bank all OUT data-out from column n. OUT t t AC, DQSCK, and 188 Micron Technology, Inc. reserves the right to change products or specifications without notice. READ Operation T3 T3n NOP NOP ACT Bank a, Row OUT OUT ...
Page 189
... Data valid window clock transition collectively when a bank is active HP 189 Micron Technology, Inc. reserves the right to change products or specifications without notice. READ Operation T3 T3n DQSQ 2 t DQSQ ...
Page 190
... T2n Data valid Data valid window window clock transition collectively when a bank is active HP QHS. 190 Micron Technology, Inc. reserves the right to change products or specifications without notice. READ Operation T3n 2,3 t 2,3 DQSQ ...
Page 191
... NOP NOP DQSCK RPRE T2n DQSQ after DQS transitions, regardless of 191 Micron Technology, Inc. reserves the right to change products or specifications without notice. READ Operation T4 T4n T5 T5n NOP NOP NOP t DQSCK T3n T4n DQSQ window ...
Page 192
... NAND Flash and LPDDR PoP (TI OMAP) MCP DQSS [MAX]) might not be obvious, they have also been included. Fig- 192 Micron Technology, Inc. reserves the right to change products or specifications without notice. WRITE Operation t WTR are satisfied DQSS for a burst of 4. ...
Page 193
... WPRES WPRE Transitioning Data t DQSS (MIN). t DQSS (MAX). 193 Micron Technology, Inc. reserves the right to change products or specifications without notice. WRITE Operation T2n DSS t WPST Don’t Care © 2009 Micron Technology, Inc. All rights reserved. ...
Page 194
... RCD DQSS (NOM) t RAS t t WPRE WPRES data-in from column n. IN 194 Micron Technology, Inc. reserves the right to change products or specifications without notice. WRITE Operation T5 T5n NOP NOP NOP DQSL DQSH ...
Page 195
... Don’t Care b = data-in for column b. IN 195 WRITE Operation T2 T2n T3 NOP NOP b+2 b b+2 b b+1 b+2 b+3 Transitioning Data Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2009 Micron Technology, Inc. All rights reserved. ...
Page 196
... T2n NOP NOP WRITE Bank, Col b+1 b+2 b+3 b (n) = data-in for column b (n). IN 196 Micron Technology, Inc. reserves the right to change products or specifications without notice. WRITE Operation T3 T3n T4 T4n T5 NOP NOP n+1 n+2 n+3 Don’t Care ...
Page 197
... Col b’ x x’ data-in for column b ( g). IN 197 Micron Technology, Inc. reserves the right to change products or specifications without notice. WRITE Operation T3 T3n T4 T4n T5 T5n 1,2 1,2 WRITE NOP Bank, Col ...
Page 198
... b+1 b+2 b data-in for column data-out for column n. IN OUT 198 Micron Technology, Inc. reserves the right to change products or specifications without notice. WRITE Operation T5n T4 T5 READ NOP 4 Bank a, Col OUT OUT ...
Page 199
... data-in for column data-out for column n. IN OUT 199 Micron Technology, Inc. reserves the right to change products or specifications without notice. WRITE Operation T6 T6n T4 T5 T5n NOP NOP NOP OUT OUT ...
Page 200
... WTR Bank a, Col data-in for column data-out for column n. IN OUT 200 Micron Technology, Inc. reserves the right to change products or specifications without notice. WRITE Operation T4 T5 T5n T6 T6n NOP NOP NOP OUT OUT n ...