MT29C4G48MAZAPAKD-5 E IT Micron, MT29C4G48MAZAPAKD-5 E IT Datasheet - Page 214

• Manufacturer Part Number: MT29C4G48MAZAPAKD-5 E IT
• Manufacturer: Micron

Figure 147: Power-Down Mode (Active or Precharge)
Deep Power-Down
PDF: 09005aef83ba4387
168ball_nand_lpddr_j42p_j4z2_j4z3_omap.pdf – Rev. H 3/11
Command
Address
DQS
CK#
CKE
DM
DQ
CK
No read/write
access in progress
t
t
t
IS
IS
IS
Valid
Valid
Notes:
T0
t
t
IH
t
2
IH
IH
Deep power-down (DPD) is an operating mode used to achieve maximum power reduc-
tion by eliminating power to the memory array. Data will not be retained after the
device enters DPD mode.
Before entering DPD mode the device must be in the all banks idle state with no activity
on the data bus (
LOW with RAS# and CAS# HIGH at the rising edge of the clock while CKE is LOW. CKE
must be held LOW to maintain DPD mode. The clock must be stable prior to exiting
DPD mode. To exit DPD mode, assert CKE HIGH with either a NOP or DESELECT com-
mand present on the command bus. After exiting DPD mode, a full DRAM initialization
sequence is required.
t
CK
1.
2. If this command is a PRECHARGE (or if the device is already in the idle state), then the
3. No column accesses can be in progress when power-down is entered.
power-down
t
HIGH at Ta2 (exit power-down).
power-down mode shown is precharge power-down. If this command is an ACTIVE (or if
at least 1 row is already active), then the power-down mode shown is active power-down.
t
CKE applies if CKE goes LOW at Ta2 (entering power-down);
IS
Enter
mode
NOP
T1
3
t
CH
Must not exceed refresh device limits
t
168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP
RP time must be met). DPD mode is entered by holding CS# and WE#
t
CL
T2
(
(
(
(
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)
(
)
(
)
(
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(
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(
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)
)
)
)
(
(
(
(
(
(
(
(
)
(
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(
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(
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(
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(
)
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)
)
)
)
t
CKE
214
Ta0
Micron Technology, Inc. reserves the right to change products or specifications without notice.
power-down
mode
NOP
Ta1
Exit
t
t
CKE
XP
1
1
© 2009 Micron Technology, Inc. All rights reserved.
Valid
Valid
t
Ta2
XP applies if CKE remains
Power-Down
Don’t Care
Tb1