MT29C4G48MAZAPAKD-5 E IT Micron, MT29C4G48MAZAPAKD-5 E IT Datasheet - Page 133

• Manufacturer Part Number: MT29C4G48MAZAPAKD-5 E IT
• Manufacturer: Micron

Figure 100: INTERNAL DATA MOVE (85h-10h) with Random Data Input with Internal ECC Enabled
Figure 101: ERASE BLOCK Operation
PDF: 09005aef83ba4387
168ball_nand_lpddr_j42p_j4z2_j4z3_omap.pdf – Rev. H 3/11
I/O[7:0]
I/O[7:0]
R/B#
WE#
RDY
CLE
ALE
CE#
RE#
00h
Source address
(5 cycles)
Address
t
WC
60h
add 1
35h
Row
Row address
t
R_ECC
add 2
Row
SR bit 0 = 0 READ successful
SR bit 1 = 0 READ error
70h
add 3
Row
Status
168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP
00h
D0h
t
WB
D
D
OUT
OUT
133
Busy
t
BERS
Asynchronous Interface Timing Diagrams
is optional
85h
Destination address
Micron Technology, Inc. reserves the right to change products or specifications without notice.
(5 cycles)
READ STATUS
Address
command
70h
Data
(Unlimitted repetitions are possible)
t
WHR
85h
Column address 1, 2
I/O0 = 0, Pass
I/O0 = 1, Fail
(2 cycles)
Address
Status
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Data
10h
t
PROG_ECC
Don’t Care
70h