MT29C4G48MAZAPAKD-5 E IT Micron, MT29C4G48MAZAPAKD-5 E IT Datasheet - Page 202

• Manufacturer Part Number: MT29C4G48MAZAPAKD-5 E IT
• Manufacturer: Micron

Figure 138: WRITE-to-PRECHARGE – Interrupting
PDF: 09005aef83ba4387
168ball_nand_lpddr_j42p_j4z2_j4z3_omap.pdf – Rev. H 3/11
Command
Address
t
t
t
DQSS (NOM)
DQSS (MIN)
DQSS (MAX)
DQS
DQS
DQS
DQ
DQ
DQ
CK#
DM
DM
DM
CK
1
5
6
5
6
5
6
WRITE
Bank a,
Col b
T0
Notes:
t
t
t
2
DQSS
DQSS
DQSS
1. An interrupted burst of 8 is shown; two data elements are written.
2. A10 is LOW with the WRITE command (auto precharge is disabled).
3. PRE = PRECHARGE.
4.
5. DQS is required at T4 and T4n to register DM.
6. D
D
b
IN
t
WR is referenced from the first positive CK edge after the last data-in pair.
NOP
T1
IN
D
b
IN
b = data-in for column b.
b + 1
D
D
b
IN
IN
T1n
b + 1
D
IN
b + 1
D
168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP
IN
NOP
T2
T2n
202
t
WR
T3
NOP
4
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T3n
(a or all)
PRE
T4
Bank
3
Don’t Care
T4n
T5
NOP
© 2009 Micron Technology, Inc. All rights reserved.
WRITE Operation
Transitioning Data
T6
NOP