MT29C4G48MAZAPAKD-5 E IT Micron, MT29C4G48MAZAPAKD-5 E IT Datasheet - Page 197

• Manufacturer Part Number: MT29C4G48MAZAPAKD-5 E IT
• Manufacturer: Micron

Figure 133: Random WRITE Cycles
PDF: 09005aef83ba4387
168ball_nand_lpddr_j42p_j4z2_j4z3_omap.pdf – Rev. H 3/11
Command
Address
DQ
DQS
CK#
DM
CK
3,4
Notes:
WRITE
Bank,
Col b
T0
1,2
t
1. Each WRITE command can be to any bank.
2. Programmed BL = 2, 4, 8, or 16 in cases shown.
3. D
4. b' (or x, n, a, g) = the next data-in following D
DQSS (NOM)
med burst order.
IN
b (or x, n, a, g) = data-in for column b (or x, n, a, g).
WRITE
Bank,
Col x
D
T1
b
IN
1,2
168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP
T1n
D
b’
IN
WRITE
Bank,
Col n
T2
D
x
IN
197
1,2
T2n
D
x’
IN
WRITE
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Bank,
Col a
D
T3
n
IN
1,2
T3n
D
Don’t Care
n’
IN
IN
b (x, n, a, g) according to the program-
WRITE
Bank,
Col g
T4
D
a
IN
1,2
T4n
D
a’
IN
Transitioning Data
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WRITE Operation
NOP
D
T5
g
IN
T5n
D
g’
IN