MT29C4G48MAZAPAKD-5 E IT Micron, MT29C4G48MAZAPAKD-5 E IT Datasheet - Page 181

• Manufacturer Part Number: MT29C4G48MAZAPAKD-5 E IT
• Manufacturer: Micron

READ Operation
PDF: 09005aef83ba4387
168ball_nand_lpddr_j42p_j4z2_j4z3_omap.pdf – Rev. H 3/11
READ burst operations are initiated with a READ command, as shown in Figure 106
(page 159). The starting column and bank addresses are provided with the READ com-
mand, and auto precharge is either enabled or disabled for that burst access. If auto
precharge is enabled, the row being accessed is precharged at the completion of the
burst. For the READ commands used in the following illustrations, auto precharge is
disabled.
During READ bursts, the valid data-out element from the starting column address will
be available following the CL after the READ command. Each subsequent data-out ele-
ment will be valid nominally at the next positive or negative clock edge. Figure 118
(page 182) shows general timing for each possible CL setting.
DQS is driven by the device along with output data. The initial LOW state on DQS is
known as the read preamble; the LOW state coincident with the last data-out element is
known as the read postamble. The READ burst is considered complete when the read
postamble is satisfied.
Upon completion of a burst, assuming no other commands have been initiated, the DQ
will go to High-Z. A detailed explanation of
window hold), and the valid data window is depicted in Figure 125 (page 189) and Fig-
ure 126 (page 190). A detailed explanation of
t
Data from any READ burst can be truncated by a READ or WRITE command to the
same or alternate bank, by a BURST TERMINATE command, or by a PRECHARGE com-
mand to the same bank, provided that the auto precharge mode was not activated.
Data from any READ burst can be concatenated with or truncated with data from a sub-
sequent READ command. In either case, a continuous flow of data can be maintained.
The first data element from the new burst either follows the last element of a completed
burst or the last desired data element of a longer burst that is being truncated. The new
READ command should be issued x cycles after the first READ command, where x
equals the number of desired data element pairs (pairs are required by the 2n-prefetch
architecture). This is shown in Figure 119 (page 183).
A READ command can be initiated on any clock cycle following a previous READ com-
mand. Nonconsecutive read data is shown in Figure 120 (page 184). Full-speed random
read accesses within a page (or pages) can be performed as shown in Figure 121
(page 185).
Data from any READ burst can be truncated with a BURST TERMINATE command, as
shown in Figure 122 (page 186). The BURST TERMINATE latency is equal to the READ
(CAS) latency; for example, the BURST TERMINATE command should be issued x cy-
cles after the READ command, where x equals the number of desired data element pairs
(pairs are required by the 2n-prefetch architecture).
Data from any READ burst must be completed or truncated before a subsequent WRITE
command can be issued. If truncation is necessary, the BURST TERMINATE command
must be used, as shown in Figure 123 (page 187). A READ burst can be followed by, or
truncated with, a PRECHARGE command to the same bank, provided that auto pre-
charge was not activated. The PRECHARGE command should be issued x cycles after
the READ command, where x equals the number of desired data element pairs. This is
shown in Figure 124 (page 188). Following the PRECHARGE command, a subsequent
AC (data-out transition skew to CK) is depicted in Figure 127 (page 191).
168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP
181
Micron Technology, Inc. reserves the right to change products or specifications without notice.
t
DQSQ (valid data-out skew),
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DQSCK (DQS transition skew to CK) and
© 2009 Micron Technology, Inc. All rights reserved.
READ Operation
t
QH (data-out