MT29C4G48MAZAPAKD-5 E IT Micron, MT29C4G48MAZAPAKD-5 E IT Datasheet - Page 100

• Manufacturer Part Number: MT29C4G48MAZAPAKD-5 E IT
• Manufacturer: Micron

Two-Plane Operations
Two-Plane Addressing
PDF: 09005aef83ba4387
168ball_nand_lpddr_j42p_j4z2_j4z3_omap.pdf – Rev. H 3/11
Each NAND Flash logical unit (LUN) is divided into multiple physical planes. Each
plane contains a cache register and a data register independent of the other planes. The
planes are addressed via the low-order block address bits. Specific details are provided
in Device and Array Organization.
Two-plane operations make better use of the NAND Flash arrays on these physical
planes by performing concurrent READ, PROGRAM, or ERASE operations on multiple
planes, significantly improving system performance. Two-plane operations must be of
the same type across the planes; for example, it is not possible to perform a PROGRAM
operation on one plane with an ERASE operation on another.
When issuing two-plane program or erase operations, use the READ STATUS (70h) com-
mand and check whether the previous operation(s) failed. If the READ STATUS (70h)
command indicates that an error occurred (FAIL = 1 and/or FAILC = 1), use the READ
STATUS ENHANCED (78h) command to determine which plane operation failed.
Two-plane commands require multiple, five-cycle addresses, one address per operation-
al plane. For a given two-plane operation, these addresses are subject to the following
requirements:
• The LUN address bit(s) must be identical for all of the issued addresses.
• The plane select bit, BA[6], must be different for each issued address.
• The page address bits, PA[5:0], must be identical for each issued address.
The READ STATUS (70h) command should be used following two-plane program page
and erase block operations on a single die (LUN).
168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP
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Two-Plane Operations
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