MT29C4G48MAZAPAKD-5 E IT Micron, MT29C4G48MAZAPAKD-5 E IT Datasheet - Page 88
MT29C4G48MAZAPAKD-5 E IT
Manufacturer Part Number
MT29C4G48MAZAPAKD-5 E IT
Description
Manufacturer
Micron
Datasheet
1.MT29C4G48MAZAPAKD-5_IT.pdf
(218 pages)
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Table 22: Block Lock Address Cycle Assignments
Figure 60: UNLOCK Operation
PDF: 09005aef83ba4387
168ball_nand_lpddr_j42p_j4z2_j4z3_omap.pdf – Rev. H 3/11
ALE Cycle
First
Second
Third
I/O[15:8]
LOW
LOW
LOW
Notes:
1
WE#
R/B#
BA15
LOW
I/Ox
WP#
CE#
ALE
RE#
I/O7
CLE
BA7
1. I/O[15:8] is applicable only for x16 devices.
2. Invert area bit is applicable for 24h command; it may be LOW or HIGH for 23h command.
Unlock
BA14
LOW
I/O6
BA6
23h
168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP
add 1
Block
BA13
LOW
LOW
I/O5
Lower boundary
add 2
Block
88
BA12
LOW
LOW
I/O4
Block
add 3
Micron Technology, Inc. reserves the right to change products or specifications without notice.
BA11
LOW
LOW
I/O3
24h
BA10
LOW
LOW
I/O2
add 1
Block
Upper boundary
© 2009 Micron Technology, Inc. All rights reserved.
Block Lock Feature
add 2
Block
BA17
LOW
I/O1
BA9
add 3
Block
Invert area bit
BA16
I/O0
BA8
2
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