MT29C4G48MAZAPAKD-5 E IT Micron, MT29C4G48MAZAPAKD-5 E IT Datasheet - Page 8

• Manufacturer Part Number: MT29C4G48MAZAPAKD-5 E IT
• Manufacturer: Micron

List of Figures
Figure 1: PoP Block Diagram ........................................................................................................................... 1
Figure 2: Part Number Chart ............................................................................................................................ 2
Figure 3: 168-Ball VFBGA (NAND x8, x16; LPDDR x32) Ball Assignments ......................................................... 12
Figure 4: 168-Ball (Single LPDDR) Functional Block Diagram .......................................................................... 17
Figure 5: 168-Ball (Dual LPDDR) Functional Block Diagram ........................................................................... 18
Figure 6: 168-Ball VFBGA (Package Code: JG) ................................................................................................. 19
Figure 7: 168-Ball VFBGA (Package Code: JV) .................................................................................................. 20
Figure 8: 168-Ball WFBGA (Package Code: KQ) ............................................................................................... 21
Figure 9: NAND Flash Die (LUN) Functional Block Diagram ........................................................................... 24
Figure 10: Array Organization – MT29F4G08 (x8) ............................................................................................ 25
Figure 11: Array Organization – MT29F4G16 (x16) .......................................................................................... 26
Figure 12: Array Organization – MT29F8G08 (x8) ............................................................................................ 27
Figure 13: Array Organization – MT29F8G16 (x16) .......................................................................................... 28
Figure 14: Asynchronous Command Latch Cycle ............................................................................................ 30
Figure 15: Asynchronous Address Latch Cycle ................................................................................................ 31
Figure 16: Asynchronous Data Input Cycles ................................................................................................... 32
Figure 17: Asynchronous Data Output Cycles ................................................................................................. 33
Figure 18: Asynchronous Data Output Cycles (EDO Mode) ............................................................................. 34
Figure 19: READ/BUSY# Open Drain ............................................................................................................. 35
Figure 20:
Figure 21:
Figure 22: I
Figure 23: I
Figure 24: TC vs. Rp ....................................................................................................................................... 38
Figure 25: R/B# Power-On Behavior ............................................................................................................... 39
Figure 26: RESET (FFh) Operation ................................................................................................................. 43
Figure 27: READ ID (90h) with 00h Address Operation .................................................................................... 44
Figure 28: READ ID (90h) with 20h Address Operation .................................................................................... 44
Figure 29: READ PARAMETER (ECh) Operation .............................................................................................. 47
Figure 30: READ UNIQUE ID (EDh) Operation ............................................................................................... 51
Figure 31: SET FEATURES (EFh) Operation .................................................................................................... 53
Figure 32: GET FEATURES (EEh) Operation ................................................................................................... 54
Figure 33: READ STATUS (70h) Operation ...................................................................................................... 58
Figure 34: READ STATUS ENHANCED (78h) Operation .................................................................................. 59
Figure 35: RANDOM DATA READ (05h-E0h) Operation .................................................................................. 60
Figure 36: RANDOM DATA READ TWO-PLANE (06h-E0h) Operation .............................................................. 61
Figure 37: RANDOM DATA INPUT (85h) Operation ........................................................................................ 62
Figure 38: PROGRAM FOR INTERNAL DATA INPUT (85h) Operation .............................................................. 64
Figure 39: READ PAGE (00h-30h) Operation ................................................................................................... 68
Figure 40: READ PAGE (00h-30h) Operation with Internal ECC Enabled .......................................................... 68
Figure 41: READ PAGE CACHE SEQUENTIAL (31h) Operation ........................................................................ 69
Figure 42: READ PAGE CACHE RANDOM (00h-31h) Operation ....................................................................... 70
Figure 43: READ PAGE CACHE LAST (3Fh) Operation ..................................................................................... 71
Figure 44: READ PAGE TWO-PLANE (00h-00h-30h) Operation ....................................................................... 73
Figure 45: PROGRAM PAGE (80h-10h) Operation ........................................................................................... 75
Figure 46: PROGRAM PAGE CACHE (80h–15h) Operation (Start) .................................................................... 77
Figure 47: PROGRAM PAGE CACHE (80h–15h) Operation (End) ..................................................................... 77
Figure 48: PROGRAM PAGE TWO-PLANE (80h–11h) Operation ...................................................................... 79
Figure 49: ERASE BLOCK (60h-D0h) Operation .............................................................................................. 80
Figure 50: ERASE BLOCK TWO-PLANE (60h–D1h) Operation ......................................................................... 81
PDF: 09005aef83ba4387
168ball_nand_lpddr_j42p_j4z2_j4z3_omap.pdf – Rev. H 3/11
t
t
Fall and
Fall and
OL
OL
vs. Rp (V
vs. Rp (1.8V V
t
t
Rise (3.3V V
Rise (1.8V V
CC
= 3.3V V
CC
) ....................................................................................................................... 37
CC
CC
CC
) ................................................................................................................ 36
) ................................................................................................................ 36
) .............................................................................................................. 37
168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP
8
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2009 Micron Technology, Inc. All rights reserved.
Features