MT29C4G48MAZAPAKD-5 E IT Micron, MT29C4G48MAZAPAKD-5 E IT Datasheet - Page 78

• Manufacturer Part Number: MT29C4G48MAZAPAKD-5 E IT
• Manufacturer: Micron

PROGRAM PAGE TWO-PLANE (80h-11h)
PDF: 09005aef83ba4387
168ball_nand_lpddr_j42p_j4z2_j4z3_omap.pdf – Rev. H 3/11
The PROGRAM PAGE TWO-PLANE (80h-11h) command enables the host to input data
to the addressed plane's cache register and queue the cache register to ultimately be
moved to the NAND Flash array. This command can be issued one or more times. Each
time a new plane address is specified that plane is also queued for data transfer. To in-
put data for the final plane and to begin the program operation for all previously
queued planes, issue either the PROGRAM PAGE (80h-10h) command or the PROGRAM
PAGE CACHE (80h-15h) command. All of the queued planes will move the data to the
NAND Flash array. This command is accepted by the die (LUN) when it is ready
(RDY = 1).
To input a page to the cache register and queue it to be moved to the NAND Flash array
at the block and page address specified, write 80h to the command register. Unless this
command has been preceded by a PROGRAM PAGE TWO-PLANE (80h-11h) command,
issuing the 80h to the command register clears all of the cache registers' contents on the
selected target. Write five address cycles containing the column address and row ad-
dress; data input cycles follow. Serial data is input beginning at the column address
specified. At any time during the data input cycle, the RANDOM DATA INPUT (85h)
and PROGRAM FOR INTERNAL DATA INPUT (85h) commands can be issued. When
data input is complete, write 11h to the command register. The selected die (LUN) will
go busy (RDY = 0, ARDY = 0) for
To determine the progress of
alternatively, the status operations (70h, 78h) can be used. When the LUN's status
shows that it is ready (RDY = 1), additional PROGRAM PAGE TWO-PLANE (80h-11h)
commands can be issued to queue additional planes for data transfer. Alternatively, the
PROGRAM PAGE (80h-10h) or PROGRAM PAGE CACHE (80h-15h) commands can be
issued.
When the PROGRAM PAGE (80h-10h) command is used as the final command of a two-
plane program operation, data is transferred from the cache registers to the NAND
Flash array for all of the addressed planes during
(RDY = 1, ARDY = 1), the host should check the status of the FAIL bit for each of the
planes to verify that programming completed successfully.
When the PROGRAM PAGE CACHE (80h-15h) command is used as the final command
of a program cache two-plane operation, data is transferred from the cache registers to
the data registers after the previous array operations finish. The data is then moved
from the data registers to the NAND Flash array for all of the addressed planes. This
occurs during
each of the planes from the previous program cache operation, if any, to verify that pro-
gramming completed successfully.
For the PROGRAM PAGE TWO-PLANE (80h-11h), PROGRAM PAGE (80h-10h), and PRO-
GRAM PAGE CACHE (80h-15h) commands, see Two-Plane Operations for two-plane
addressing requirements.
t
CBSY. After
168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP
t
CBSY, the host should check the status of the FAILC bit for
78
t
DBSY, the host can monitor the target's R/B# signal or,
t
DBSY.
Micron Technology, Inc. reserves the right to change products or specifications without notice.
t
PROG. When the die (LUN) is ready
Program Operations
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