MT29C4G48MAZAPAKD-5 E IT Micron, MT29C4G48MAZAPAKD-5 E IT Datasheet - Page 177

• Manufacturer Part Number: MT29C4G48MAZAPAKD-5 E IT
• Manufacturer: Micron

Partial-Array Self Refresh
Output Drive Strength
PDF: 09005aef83ba4387
168ball_nand_lpddr_j42p_j4z2_j4z3_omap.pdf – Rev. H 3/11
For further power savings during self refresh, the partial-array self refresh (PASR) fea-
ture enables the controller to select the amount of memory to be refreshed during self
refresh. The refresh options include:
• Full array: banks 0, 1, 2, and 3
• One-half array: banks 0 and 1
• One-quarter array: bank 0
• One-eighth array: bank 0 with row address most significant bit (MSB) = 0
• One-sixteenth array: bank 0 with row address MSB = 0 and row address MSB - 1 = 0
READ and WRITE commands can still be issued to the full array during standard opera-
tion, but only the selected regions of the array will be refreshed during self refresh. Data
in regions that are not selected will be lost.
Because the device is designed for use in smaller systems that are typically point-to-
point connections, an option to control the drive strength of the output buffers is
provided. Drive strength should be selected based on the expected loading of the mem-
ory bus. The output driver settings are 25Ω, 37Ω, and 55Ω internal impedance for full,
three-quarter, and one-half drive strengths, respectively.
168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP
177
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