MT29C4G48MAZAPAKD-5 E IT Micron, MT29C4G48MAZAPAKD-5 E IT Datasheet - Page 169

• Manufacturer Part Number: MT29C4G48MAZAPAKD-5 E IT
• Manufacturer: Micron

Initialization
PDF: 09005aef83ba4387
168ball_nand_lpddr_j42p_j4z2_j4z3_omap.pdf – Rev. H 3/11
Prior to normal operation, the device must be powered up and initialized in a prede-
fined manner. Using initialization procedures other than those specified will result in
undefined operation.
If there is an interruption to the device power, the device must be re-initialized using
the initialization sequence described below to ensure proper functionality of the device.
To properly initialize the device, this sequence must be followed:
After steps 1–10 are completed, the device has been properly initialized and is ready to
receive any valid command.
10. Issue NOP or DESELECT commands for at least
1. The core power (V
2. When power supply voltages are stable and the CKE has been driven HIGH, it is
3. When the clock is stable, a 200μs minimum delay is required by the Mobile
4. Issue a PRECHARGE ALL command.
5. Issue NOP or DESELECT commands for at least
6. Issue an AUTO REFRESH command followed by NOP or DESELECT commands
7. Using the LOAD MODE REGISTER command, load the standard mode register as
8. Issue NOP or DESELECT commands for at least
9. Using the LOAD MODE REGISTER command, load the extended mode register to
It is recommended that V
must never exceed V
HIGH (see Figure 111 (page 170)). Alternatively, initialization can be completed
with CKE LOW provided that CKE transitions HIGH
(page 171)).
safe to apply the clock.
LPDDR prior to applying an executable command. During this time, NOP or DESE-
LECT commands must be issued on the command bus.
for at least
or DESELECT commands for at least
must be issued. Typically, both of these commands are issued at this stage as de-
scribed above.
desired.
the desired operating modes. Note that the sequence in which the standard and
extended mode registers are programmed is not critical.
t
168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP
RFC time. Issue a second AUTO REFRESH command followed by NOP
DD
DD
) and I/O power (V
. Standard initialization requires that CKE be asserted
169
DD
and V
Micron Technology, Inc. reserves the right to change products or specifications without notice.
DDQ
t
RFC time. Two AUTO REFRESH commands
be from the same power source, or V
DDQ
) must be brought up simultaneously.
t
t
t
RP time.
MRD time.
MRD time.
t
IS prior to T0 (see Figure 112
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Initialization
DDQ