MT29C4G48MAZAPAKD-5 E IT Micron, MT29C4G48MAZAPAKD-5 E IT Datasheet - Page 110

• Manufacturer Part Number: MT29C4G48MAZAPAKD-5 E IT
• Manufacturer: Micron

Error Management
PDF: 09005aef83ba4387
168ball_nand_lpddr_j42p_j4z2_j4z3_omap.pdf – Rev. H 3/11
Each NAND Flash die (LUN) is specified to have a minimum number of valid blocks
(NVB) of the total available blocks. This means the die (LUNs) could have blocks that
are invalid when shipped from the factory. An invalid block is one that contains at least
one page that has more bad bits than can be corrected by the minimum required ECC.
Additional blocks can develop with use. However, the total number of available blocks
per die (LUN) will not fall below NVB during the endurance life of the product.
Although NAND Flash memory devices could contain bad blocks, they can be used
quite reliably in systems that provide bad block management and error-correction algo-
rithms. This type of software environment ensures data integrity.
Internal circuitry isolates each block from other blocks, so the presence of a bad block
does not affect the operation of the rest of the NAND Flash array.
NAND Flash devices are shipped from the factory erased. The factory identifies invalid
blocks before shipping by attempting to program the bad block mark into every loca-
tion in the first page of each invalid block. It may not be possible to program every
location with the bad block mark. However, the first spare area location in each bad
block is guaranteed to contain the bad block mark. This method is compliant with ONFI
Factory Defect Mapping requirements. See the following table for the first spare area
location and the bad block mark.
System software should check the first spare area location on the first page of each
block prior to performing any PROGRAM or ERASE operations on the NAND Flash de-
vice. A bad block table can then be created, enabling system software to map around
these areas. Factory testing is performed under worst-case conditions. Because invalid
blocks could be marginal, it may not be possible to recover this information if the block
is erased.
Over time, some memory locations may fail to program or erase properly. In order to
ensure that data is stored properly over the life of the NAND Flash device, the following
precautions are required:
• Always check status after a PROGRAM or ERASE operation
• Under typical conditions, use the minimum required ECC (see table below)
• Use bad block management and wear-leveling algorithms
Table 24: Error Management Details
Description
Minimum number of valid blocks (NVB) per LUN
Total available blocks per LUN
First spare area location
Bad-block mark
Minimum required ECC
The first block (physical block address 00h) for each CE# is guaranteed to be valid
with ECC when shipped from the factory.
168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP
110
Micron Technology, Inc. reserves the right to change products or specifications without notice.
Requirement
4016
4096
x8: byte 2048
x16: word 1024
x8: 00h
x16: 0000h
4-bit ECC per 528 bytes
© 2009 Micron Technology, Inc. All rights reserved.
Error Management