MT29C4G48MAZAPAKD-5 E IT Micron, MT29C4G48MAZAPAKD-5 E IT Datasheet - Page 27

• Manufacturer Part Number: MT29C4G48MAZAPAKD-5 E IT
• Manufacturer: Micron

Figure 12: Array Organization – MT29F8G08 (x8)
Table 8: Array Addressing – MT29F8G08 (x8)
PDF: 09005aef83ba4387
168ball_nand_lpddr_j42p_j4z2_j4z3_omap.pdf – Rev. H 3/11
Second
Fourth
Cycle
Cache Register
2048 blocks
4096 blocks
Third
Fifth
First
Data Register
per plane
per die
BA15
LOW
LOW
numbered blocks
CA7
BA7
I/07
Plane 0: even-
(0, 2, 4, 6, ...,
4092, 4094)
1 block
2048
2048
Notes:
Note:
2112 bytes
1
64
64
1. Die 0, Plane 0: BA18 = 0; BA6 = 0. Die 0, Plane 1: BA18 = 0; BA6 = 1.
1. CAx = column address; PAx = page address; BAx = block address.
2. If CA11 is 1, then CA[10:6] must be 0.
3. Die address boundary: 0 = 0–4Gb; 1 = 4Gb–8Gb.
BA14
LOW
LOW
I/06
CA6
BA6
Die 1, Plane 0: BA18 = 1; BA6 = 0. Die 1, Plane 1: BA18 = 1; BA6 = 1.
numbered blocks
Die 0
Plane 1: odd-
(1, 3, 5, 7, ...,
4093, 4095)
1 block
2048
2048
2112 bytes
BA13
LOW
LOW
I/05
CA5
PA5
168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP
64
64
numbered blocks
(4096, 4098, ...,
Plane 0: even-
8188, 8190)
1 block
2048
2048
2112 bytes
BA12
LOW
LOW
CA4
I/04
PA4
27
64
64
numbered blocks
Die 1
(4097, 4099, ...,
Plane 1: odd-
Micron Technology, Inc. reserves the right to change products or specifications without notice.
8189, 8191)
1 block
2048
2048
CA11
BA11
LOW
CA3
I/03
PA3
2112 bytes
Device and Array Organization
64
64
BA18
CA10
BA10
I/02
CA2
PA2
1 page = (2K + 64 bytes)
1 block = (2K + 64) bytes x 64 pages
1 plane = (128K + 4K) bytes x 2048 blocks
1 die
1 device = 4224Mb x 2 die
3
I/O0
I/O7
© 2009 Micron Technology, Inc. All rights reserved.
= (128K + 4K) bytes
= 2112Mb
= 2112Mb x 2 planes
= 4224Mb
= 8448Mb
BA17
I/01
CA1
CA9
PA1
BA9
BA16
CA0
CA8
BA8
I/00
PA0